1 From e93b9480667cbd0e3a4276e8749279693fe239f4 Mon Sep 17 00:00:00 2001
2 From: Andy Gross <agross@codeaurora.org>
3 Date: Wed, 14 May 2014 22:49:03 -0500
4 Subject: [PATCH 136/182] ARM: ipq8064-ap148: Add i2c pinctrl nodes
6 Signed-off-by: Andy Gross <agross@codeaurora.org>
8 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 17 +++++++++++++++++
9 arch/arm/boot/dts/qcom-ipq8064.dtsi | 27 +++++++++++++++++++++++++++
10 2 files changed, 44 insertions(+)
12 diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
13 index 100b6eb..dbb546d 100644
14 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
15 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
21 + i2c4_pins: i2c4_pinmux {
22 + pins = "gpio12", "gpio13";
29 qcom,mode = <GSBI_PROT_I2C_UART>;
35 + i2c4: i2c@16380000 {
38 + clock-frequency = <200000>;
40 + pinctrl-0 = <&i2c4_pins>;
41 + pinctrl-names = "default";
46 diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
47 index 952afb7..b39c1ef 100644
48 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
49 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
51 clock-names = "core", "iface";
56 + compatible = "qcom,i2c-qup-v1.1.1";
57 + reg = <0x124a0000 0x1000>;
58 + interrupts = <0 196 0>;
60 + clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
61 + clock-names = "core", "iface";
62 + status = "disabled";
64 + #address-cells = <1>;
70 gsbi4: gsbi@16300000 {
72 clock-names = "core", "iface";
77 + compatible = "qcom,i2c-qup-v1.1.1";
78 + reg = <0x16380000 0x1000>;
79 + interrupts = <0 153 0>;
81 + clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
82 + clock-names = "core", "iface";
83 + status = "disabled";
85 + #address-cells = <1>;