1 From 7c6525a0d5cf88f9244187fbe8ee293fa4ee43c1 Mon Sep 17 00:00:00 2001
2 From: Kumar Gala <galak@codeaurora.org>
3 Date: Mon, 12 May 2014 19:36:23 -0500
4 Subject: [PATCH 139/182] ARM: dts: msm: Add PCIe related nodes for
8 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 38 ++++++++++++
9 arch/arm/boot/dts/qcom-ipq8064.dtsi | 93 ++++++++++++++++++++++++++++++
10 2 files changed, 131 insertions(+)
12 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
13 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
18 + pcie1_pins: pcie1_pinmux {
21 + drive-strength = <2>;
26 + pcie2_pins: pcie2_pinmux {
29 + drive-strength = <2>;
36 pins = "gpio18", "gpio19", "gpio21";
44 + reset-gpio = <&qcom_pinmux 3 0>;
45 + pinctrl-0 = <&pcie1_pins>;
46 + pinctrl-names = "default";
48 + ranges = <0x00000000 0 0x00000000 0x0ff00000 0 0x00100000 /* configuration space */
49 + 0x81000000 0 0 0x0fe00000 0 0x00100000 /* downstream I/O */
50 + 0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
55 + reset-gpio = <&qcom_pinmux 48 0>;
56 + pinctrl-0 = <&pcie2_pins>;
57 + pinctrl-names = "default";
59 + ranges = <0x00000000 0 0x00000000 0x31f00000 0 0x00100000 /* configuration space */
60 + 0x81000000 0 0 0x31e00000 0 0x00100000 /* downstream I/O */
61 + 0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
65 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
66 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
69 #include "skeleton.dtsi"
70 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
71 +#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
72 #include <dt-bindings/soc/qcom,gsbi.h>
81 + compatible = "qcom,pcie-ipq8064";
82 + reg = <0x1b500000 0x1000
86 + reg-names = "base", "elbi", "parf";
88 + #address-cells = <3>;
90 + device_type = "pci";
91 + interrupts = <0 35 0x0
96 + resets = <&gcc PCIE_ACLK_RESET>,
97 + <&gcc PCIE_HCLK_RESET>,
98 + <&gcc PCIE_POR_RESET>,
99 + <&gcc PCIE_PCI_RESET>,
100 + <&gcc PCIE_PHY_RESET>;
101 + reset-names = "axi", "ahb", "por", "pci", "phy";
103 + clocks = <&gcc PCIE_A_CLK>,
105 + <&gcc PCIE_PHY_CLK>;
106 + clock-names = "core", "iface", "phy";
107 + status = "disabled";
111 + compatible = "qcom,pcie-ipq8064";
112 + reg = <0x1b700000 0x1000
116 + reg-names = "base", "elbi", "parf";
118 + #address-cells = <3>;
120 + device_type = "pci";
122 + interrupts = <0 57 0x0
127 + resets = <&gcc PCIE_1_ACLK_RESET>,
128 + <&gcc PCIE_1_HCLK_RESET>,
129 + <&gcc PCIE_1_POR_RESET>,
130 + <&gcc PCIE_1_PCI_RESET>,
131 + <&gcc PCIE_1_PHY_RESET>;
132 + reset-names = "axi", "ahb", "por", "pci", "phy";
134 + clocks = <&gcc PCIE_1_A_CLK>,
135 + <&gcc PCIE_1_H_CLK>,
136 + <&gcc PCIE_1_PHY_CLK>;
137 + clock-names = "core", "iface", "phy";
138 + status = "disabled";
142 + compatible = "qcom,pcie-ipq8064";
143 + reg = <0x1b900000 0x1000
147 + reg-names = "base", "elbi", "parf";
149 + #address-cells = <3>;
151 + device_type = "pci";
153 + interrupts = <0 71 0x0
158 + resets = <&gcc PCIE_2_ACLK_RESET>,
159 + <&gcc PCIE_2_HCLK_RESET>,
160 + <&gcc PCIE_2_POR_RESET>,
161 + <&gcc PCIE_2_PCI_RESET>,
162 + <&gcc PCIE_2_PHY_RESET>;
163 + reset-names = "axi", "ahb", "por", "pci", "phy";
165 + clocks = <&gcc PCIE_2_A_CLK>,
166 + <&gcc PCIE_2_H_CLK>,
167 + <&gcc PCIE_2_PHY_CLK>;
168 + clock-names = "core", "iface", "phy";
169 + status = "disabled";