1 From 6992cf3e8900d042a845eafc11e7841f32fec0a6 Mon Sep 17 00:00:00 2001
2 From: Kumar Gala <galak@codeaurora.org>
3 Date: Thu, 12 Jun 2014 10:56:54 -0500
4 Subject: [PATCH 146/182] ARM: dts: qcom: Add SATA support for IPQ8064 and
8 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 8 ++++++++
9 arch/arm/boot/dts/qcom-ipq8064.dtsi | 30 ++++++++++++++++++++++++++++++
10 2 files changed, 38 insertions(+)
12 diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
13 index 11f7a77..c752889 100644
14 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
15 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
17 0x81000000 0 0 0x31e00000 0 0x00100000 /* downstream I/O */
18 0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
30 diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
31 index 42a651f..93c0315 100644
32 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
33 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
35 clock-names = "core", "iface", "phy";
39 + sata_phy: sata-phy@1b400000 {
40 + compatible = "qcom,ipq806x-sata-phy";
41 + reg = <0x1b400000 0x200>;
43 + clocks = <&gcc SATA_PHY_CFG_CLK>;
44 + clock-names = "cfg";
47 + status = "disabled";
51 + compatible = "qcom,ipq806x-ahci", "qcom,msm-ahci";
52 + reg = <0x29000000 0x180>;
54 + interrupts = <0 209 0x0>;
56 + clocks = <&gcc SFAB_SATA_S_H_CLK>,
59 + <&gcc SATA_RXOOB_CLK>,
60 + <&gcc SATA_PMALIVE_CLK>;
61 + clock-names = "slave_face", "iface", "core",
65 + phy-names = "sata-phy";
66 + status = "disabled";