1 From 4490cfa66379909cdddc3518c8e75b7cd26d8f69 Mon Sep 17 00:00:00 2001
2 From: Andy Gross <agross@codeaurora.org>
3 Date: Mon, 16 Jun 2014 16:53:49 -0500
4 Subject: [PATCH 151/182] ARM: ipq8064: Add nand device info
6 Signed-off-by: Andy Gross <agross@codeaurora.org>
8 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 34 ++++++++++++++++++++++++++++++
9 arch/arm/boot/dts/qcom-ipq8064.dtsi | 33 +++++++++++++++++++++++++++++
10 2 files changed, 67 insertions(+)
12 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
13 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
18 + nand_pins: nand_pins {
20 + pins = "gpio34", "gpio35", "gpio36",
21 + "gpio37", "gpio38", "gpio39",
22 + "gpio40", "gpio41", "gpio42",
23 + "gpio43", "gpio44", "gpio45",
26 + drive-strength = <10>;
34 + pins = "gpio40", "gpio41", "gpio42",
35 + "gpio43", "gpio44", "gpio45",
56 + pinctrl-0 = <&nand_pins>;
57 + pinctrl-names = "default";
61 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
62 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
65 #interrupt-cells = <2>;
66 interrupts = <0 32 0x4>;
70 intc: interrupt-controller@2000000 {
72 phy-names = "sata-phy";
76 + adm_dma: dma@18300000 {
77 + compatible = "qcom,adm";
78 + reg = <0x18300000 0x100000>;
79 + interrupts = <0 170 0>;
81 + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
82 + clock-names = "core_clk", "iface_clk";
84 + resets = <&gcc ADM0_RESET>,
85 + <&gcc ADM0_PBUS_RESET>,
86 + <&gcc ADM0_C0_RESET>,
87 + <&gcc ADM0_C1_RESET>,
88 + <&gcc ADM0_C2_RESET>;
90 + reset-names = "adm", "pbus", "c0", "c1", "c2";
92 + status = "disabled";
96 + compatible = "qcom,qcom_nand";
97 + reg = <0x1ac00000 0x800>;
98 + #address-cells = <1>;
101 + clocks = <&gcc EBI2_CLK>;
102 + clock-names = "core_clk";
105 + status = "disabled";