target/linux/ipq806x/patches/0151-ARM-ipq8064-Add-nand-device-info.patch

   1 From 4490cfa66379909cdddc3518c8e75b7cd26d8f69 Mon Sep 17 00:00:00 2001
   2 From: Andy Gross <agross@codeaurora.org>
   3 Date: Mon, 16 Jun 2014 16:53:49 -0500
   4 Subject: [PATCH 151/182] ARM: ipq8064: Add nand device info
   5
   6 Signed-off-by: Andy Gross <agross@codeaurora.org>
   7 ---
   8  arch/arm/boot/dts/qcom-ipq8064-ap148.dts |   34 ++++++++++++++++++++++++++++++
   9  arch/arm/boot/dts/qcom-ipq8064.dtsi      |   33 +++++++++++++++++++++++++++++
  10  2 files changed, 67 insertions(+)
  11
  12 diff --git a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  13 index c752889..4062eb6 100644
  14 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  15 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
  16 @@ -45,6 +45,29 @@
  17                                         bias-none;
  18                                 };
  19                         };
  20 +                       nand_pins: nand_pins {
  21 +                               mux {
  22 +                                       pins = "gpio34", "gpio35", "gpio36",
  23 +                                               "gpio37", "gpio38", "gpio39",
  24 +                                               "gpio40", "gpio41", "gpio42",
  25 +                                               "gpio43", "gpio44", "gpio45",
  26 +                                               "gpio46", "gpio47";
  27 +                                       function = "nand";
  28 +                                       drive-strength = <10>;
  29 +                                       bias-disable;
  30 +                               };
  31 +                               pullups {
  32 +                                       pins = "gpio39";
  33 +                                       bias-pull-up;
  34 +                               };
  35 +                               hold {
  36 +                                       pins = "gpio40", "gpio41", "gpio42",
  37 +                                               "gpio43", "gpio44", "gpio45",
  38 +                                               "gpio46", "gpio47";
  39 +                                       bias-bus-hold;
  40 +                               };
  41 +                       };
  42 +
  43                 };
  44
  45                 gsbi@16300000 {
  46 @@ -126,5 +149,16 @@
  47                 sata@29000000 {
  48                         status = "ok";
  49                 };
  50 +
  51 +               dma@18300000 {
  52 +                       status = "ok";
  53 +               };
  54 +
  55 +               nand@0x1ac00000 {
  56 +                       status = "ok";
  57 +
  58 +                       pinctrl-0 = <&nand_pins>;
  59 +                       pinctrl-names = "default";
  60 +               };
  61         };
  62  };
  63 diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  64 index 93c0315..d9fce15 100644
  65 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
  66 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
  67 @@ -76,6 +76,7 @@
  68                         interrupt-controller;
  69                         #interrupt-cells = <2>;
  70                         interrupts = <0 32 0x4>;
  71 +
  72                 };
  73
  74                 intc: interrupt-controller@2000000 {
  75 @@ -369,5 +370,37 @@
  76                         phy-names = "sata-phy";
  77                         status = "disabled";
  78                 };
  79 +
  80 +               adm_dma: dma@18300000 {
  81 +                       compatible = "qcom,adm";
  82 +                       reg = <0x18300000 0x100000>;
  83 +                       interrupts = <0 170 0>;
  84 +
  85 +                       clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
  86 +                       clock-names = "core_clk", "iface_clk";
  87 +
  88 +                       resets = <&gcc ADM0_RESET>,
  89 +                               <&gcc ADM0_PBUS_RESET>,
  90 +                               <&gcc ADM0_C0_RESET>,
  91 +                               <&gcc ADM0_C1_RESET>,
  92 +                               <&gcc ADM0_C2_RESET>;
  93 +
  94 +                       reset-names = "adm", "pbus", "c0", "c1", "c2";
  95 +
  96 +                       status = "disabled";
  97 +               };
  98 +
  99 +               nand@0x1ac00000 {
 100 +                       compatible = "qcom,qcom_nand";
 101 +                       reg = <0x1ac00000 0x800>;
 102 +                       #address-cells = <1>;
 103 +                       #size-cells = <1>;
 104 +
 105 +                       clocks = <&gcc EBI2_CLK>;
 106 +                       clock-names = "core_clk";
 107 +
 108 +
 109 +                       status = "disabled";
 110 +               };
 111         };
 112  };
 113 --
 114 1.7.10.4
 115