ipq806x: Add support for IPQ806x chip family
[openwrt/staging/lynxis/omap.git] / target / linux / ipq806x / patches / 0155-clk-qcom-Fix-incorrect-UTMI-DT-include-values.patch
1 From 9ab5cb48696dca02bf43170b50d1034a96fb9e85 Mon Sep 17 00:00:00 2001
2 From: Andy Gross <agross@codeaurora.org>
3 Date: Sun, 15 Jun 2014 00:39:57 -0500
4 Subject: [PATCH 155/182] clk: qcom: Fix incorrect UTMI DT include values
5
6 Corrected values for UTMI clock definitions.
7
8 Signed-off-by: Andy Gross <agross@codeaurora.org>
9 ---
10 include/dt-bindings/clock/qcom,gcc-ipq806x.h | 38 +++++++++++++-------------
11 1 file changed, 19 insertions(+), 19 deletions(-)
12
13 diff --git a/include/dt-bindings/clock/qcom,gcc-ipq806x.h b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
14 index 0fd3e8a..163ba85 100644
15 --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
16 +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
17 @@ -273,24 +273,24 @@
18 #define USB30_SLEEP_CLK 262
19 #define USB30_UTMI_SRC 263
20 #define USB30_0_UTMI_CLK 264
21 -#define USB30_1_UTMI_CLK 264
22 -#define USB30_MASTER_SRC 265
23 -#define USB30_0_MASTER_CLK 266
24 -#define USB30_1_MASTER_CLK 267
25 -#define GMAC_CORE1_CLK_SRC 268
26 -#define GMAC_CORE2_CLK_SRC 269
27 -#define GMAC_CORE3_CLK_SRC 270
28 -#define GMAC_CORE4_CLK_SRC 271
29 -#define GMAC_CORE1_CLK 272
30 -#define GMAC_CORE2_CLK 273
31 -#define GMAC_CORE3_CLK 274
32 -#define GMAC_CORE4_CLK 275
33 -#define UBI32_CORE1_CLK_SRC 276
34 -#define UBI32_CORE2_CLK_SRC 277
35 -#define UBI32_CORE1_CLK 278
36 -#define UBI32_CORE2_CLK 279
37 -#define NSSTCM_CLK_SRC 280
38 -#define NSSTCM_CLK 281
39 -#define NSS_CORE_CLK 282 /* Virtual */
40 +#define USB30_1_UTMI_CLK 265
41 +#define USB30_MASTER_SRC 266
42 +#define USB30_0_MASTER_CLK 267
43 +#define USB30_1_MASTER_CLK 268
44 +#define GMAC_CORE1_CLK_SRC 269
45 +#define GMAC_CORE2_CLK_SRC 270
46 +#define GMAC_CORE3_CLK_SRC 271
47 +#define GMAC_CORE4_CLK_SRC 272
48 +#define GMAC_CORE1_CLK 273
49 +#define GMAC_CORE2_CLK 274
50 +#define GMAC_CORE3_CLK 275
51 +#define GMAC_CORE4_CLK 276
52 +#define UBI32_CORE1_CLK_SRC 277
53 +#define UBI32_CORE2_CLK_SRC 278
54 +#define UBI32_CORE1_CLK 279
55 +#define UBI32_CORE2_CLK 280
56 +#define NSSTCM_CLK_SRC 281
57 +#define NSSTCM_CLK 282
58 +#define NSS_CORE_CLK 283 /* Virtual */
59
60 #endif
61 --
62 1.7.10.4
63