1 From 364532aeb9024d0ff7b88121f9a953f559b1c136 Mon Sep 17 00:00:00 2001
2 From: "Ivan T. Ivanov" <iivanov@mm-sol.com>
3 Date: Mon, 7 Oct 2013 10:44:57 +0300
4 Subject: [PATCH 156/182] usb: dwc3: Add Qualcomm DWC3 glue layer driver
6 DWC3 glue layer is hardware layer around Synopsys DesignWare
7 USB3 core. Its purpose is to supply Synopsys IP with required
8 clocks, voltages and interface it with the rest of the SoC.
10 Signed-off-by: Ivan T. Ivanov <iivanov@mm-sol.com>
12 drivers/usb/dwc3/Kconfig | 8 +++
13 drivers/usb/dwc3/Makefile | 1 +
14 drivers/usb/dwc3/dwc3-qcom.c | 156 ++++++++++++++++++++++++++++++++++++++++++
15 3 files changed, 165 insertions(+)
16 create mode 100644 drivers/usb/dwc3/dwc3-qcom.c
18 --- a/drivers/usb/dwc3/Kconfig
19 +++ b/drivers/usb/dwc3/Kconfig
20 @@ -59,6 +59,14 @@ config USB_DWC3_EXYNOS
21 Recent Exynos5 SoCs ship with one DesignWare Core USB3 IP inside,
22 say 'Y' or 'M' if you have one such device.
25 + tristate "Qualcomm Platforms"
27 + select USB_QCOM_DWC3_PHYS
29 + Recent Qualcomm SoCs ship with one DesignWare Core USB3 IP inside,
30 + say 'Y' or 'M' if you have one such device.
33 tristate "PCIe-based Platforms"
35 --- a/drivers/usb/dwc3/Makefile
36 +++ b/drivers/usb/dwc3/Makefile
37 @@ -31,5 +31,6 @@ endif
39 obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
40 obj-$(CONFIG_USB_DWC3_EXYNOS) += dwc3-exynos.o
41 +obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom.o
42 obj-$(CONFIG_USB_DWC3_PCI) += dwc3-pci.o
43 obj-$(CONFIG_USB_DWC3_KEYSTONE) += dwc3-keystone.o
45 +++ b/drivers/usb/dwc3/dwc3-qcom.c
47 +/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
49 + * This program is free software; you can redistribute it and/or modify
50 + * it under the terms of the GNU General Public License version 2 and
51 + * only version 2 as published by the Free Software Foundation.
53 + * This program is distributed in the hope that it will be useful,
54 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
55 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
56 + * GNU General Public License for more details.
59 +#include <linux/clk.h>
60 +#include <linux/err.h>
61 +#include <linux/io.h>
62 +#include <linux/module.h>
63 +#include <linux/of.h>
64 +#include <linux/of_platform.h>
65 +#include <linux/platform_device.h>
66 +#include <linux/regulator/consumer.h>
67 +#include <linux/usb/phy.h>
75 + struct clk *core_clk;
76 + struct clk *iface_clk;
77 + struct clk *sleep_clk;
79 + struct regulator *gdsc;
82 +static int dwc3_qcom_probe(struct platform_device *pdev)
84 + struct device_node *node = pdev->dev.of_node;
85 + struct dwc3_qcom *mdwc;
88 + mdwc = devm_kzalloc(&pdev->dev, sizeof(*mdwc), GFP_KERNEL);
92 + platform_set_drvdata(pdev, mdwc);
94 + mdwc->dev = &pdev->dev;
96 + mdwc->gdsc = devm_regulator_get(mdwc->dev, "gdsc");
98 + mdwc->core_clk = devm_clk_get(mdwc->dev, "core");
99 + if (IS_ERR(mdwc->core_clk)) {
100 + dev_dbg(mdwc->dev, "failed to get core clock\n");
101 + return PTR_ERR(mdwc->core_clk);
104 + mdwc->iface_clk = devm_clk_get(mdwc->dev, "iface");
105 + if (IS_ERR(mdwc->iface_clk)) {
106 + dev_dbg(mdwc->dev, "failed to get iface clock, skipping\n");
107 + mdwc->iface_clk = NULL;
110 + mdwc->sleep_clk = devm_clk_get(mdwc->dev, "sleep");
111 + if (IS_ERR(mdwc->sleep_clk)) {
112 + dev_dbg(mdwc->dev, "failed to get sleep clock, skipping\n");
113 + mdwc->sleep_clk = NULL;
116 + if (!IS_ERR(mdwc->gdsc)) {
117 + ret = regulator_enable(mdwc->gdsc);
119 + dev_err(mdwc->dev, "cannot enable gdsc\n");
122 + clk_prepare_enable(mdwc->core_clk);
124 + if (mdwc->iface_clk)
125 + clk_prepare_enable(mdwc->iface_clk);
127 + if (mdwc->sleep_clk)
128 + clk_prepare_enable(mdwc->sleep_clk);
130 + ret = of_platform_populate(node, NULL, NULL, mdwc->dev);
132 + dev_err(mdwc->dev, "failed to register core - %d\n", ret);
133 + dev_dbg(mdwc->dev, "failed to add create dwc3 core\n");
141 + dev_err(mdwc->dev, "disabling clocks\n");
143 + if (mdwc->sleep_clk)
144 + clk_disable_unprepare(mdwc->sleep_clk);
146 + if (mdwc->iface_clk)
147 + clk_disable_unprepare(mdwc->iface_clk);
149 + clk_disable_unprepare(mdwc->core_clk);
151 + if (!IS_ERR(mdwc->gdsc)) {
152 + ret = regulator_disable(mdwc->gdsc);
154 + dev_dbg(mdwc->dev, "cannot disable gdsc\n");
160 +static int dwc3_qcom_remove(struct platform_device *pdev)
164 + struct dwc3_qcom *mdwc = platform_get_drvdata(pdev);
166 + if (mdwc->sleep_clk)
167 + clk_disable_unprepare(mdwc->sleep_clk);
169 + if (mdwc->iface_clk)
170 + clk_disable_unprepare(mdwc->iface_clk);
172 + clk_disable_unprepare(mdwc->core_clk);
174 + if (!IS_ERR(mdwc->gdsc)) {
175 + ret = regulator_disable(mdwc->gdsc);
177 + dev_dbg(mdwc->dev, "cannot disable gdsc\n");
182 +static const struct of_device_id of_dwc3_match[] = {
183 + { .compatible = "qcom,dwc3" },
186 +MODULE_DEVICE_TABLE(of, of_dwc3_match);
188 +static struct platform_driver dwc3_qcom_driver = {
189 + .probe = dwc3_qcom_probe,
190 + .remove = dwc3_qcom_remove,
192 + .name = "qcom-dwc3",
193 + .owner = THIS_MODULE,
194 + .of_match_table = of_dwc3_match,
198 +module_platform_driver(dwc3_qcom_driver);
200 +MODULE_ALIAS("platform:qcom-dwc3");
201 +MODULE_LICENSE("GPL v2");
202 +MODULE_DESCRIPTION("DesignWare USB3 QCOM Glue Layer");