1 From 269a71c81438604d27f01ec703daa7f5e3f39e8b Mon Sep 17 00:00:00 2001
2 From: Andy Gross <agross@codeaurora.org>
3 Date: Sun, 15 Jun 2014 00:48:18 -0500
4 Subject: [PATCH 159/182] arm: ipq8064: Add USB3 DT information
6 This patch fleshes out the USB3 specific information for the IPQ8064 platform.
8 Signed-off-by: Andy Gross <agross@codeaurora.org>
10 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 29 ++++++++++
11 arch/arm/boot/dts/qcom-ipq8064.dtsi | 90 ++++++++++++++++++++++++++++++
12 2 files changed, 119 insertions(+)
14 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
15 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
17 pinctrl-0 = <&nand_pins>;
18 pinctrl-names = "default";
23 + qcom,usb-ctrl-select = <TCSR_USB_SELECT_USB3_DUAL>;
26 + phy@100f8800 { /* USB3 port 1 HS phy */
30 + phy@100f8830 { /* USB3 port 1 SS phy */
34 + phy@110f8800 { /* USB3 port 0 HS phy */
38 + phy@110f8830 { /* USB3 port 0 SS phy */
51 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
52 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
54 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
55 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
56 #include <dt-bindings/soc/qcom,gsbi.h>
57 +#include <dt-bindings/soc/qcom,tcsr.h>
60 model = "Qualcomm IPQ8064";
66 + tcsr: tcsr@1a400000 {
67 + compatible = "qcom,tcsr";
68 + reg = <0x1a400000 0x100>;
70 + status = "disabled";
73 + hs_phy_1: phy@100f8800 {
74 + compatible = "qcom,dwc3-hsphy";
75 + reg = <0x100f8800 0x30>;
76 + clocks = <&gcc USB30_1_UTMI_CLK>;
77 + clock-names = "utmi";
79 + status = "disabled";
82 + ss_phy_1: phy@100f8830 {
83 + compatible = "qcom,dwc3-ssphy";
84 + reg = <0x100f8830 0x30>;
86 + clocks = <&gcc USB30_1_MASTER_CLK>;
87 + clock-names = "ref";
89 + status = "disabled";
92 + hs_phy_0: phy@110f8800 {
93 + compatible = "qcom,dwc3-hsphy";
94 + reg = <0x110f8800 0x30>;
95 + clocks = <&gcc USB30_0_UTMI_CLK>;
96 + clock-names = "utmi";
98 + status = "disabled";
101 + ss_phy_0: phy@110f8830 {
102 + compatible = "qcom,dwc3-ssphy";
103 + reg = <0x110f8830 0x30>;
105 + clocks = <&gcc USB30_0_MASTER_CLK>;
106 + clock-names = "ref";
108 + status = "disabled";
112 + compatible = "qcom,dwc3";
113 + #address-cells = <1>;
115 + clocks = <&gcc USB30_0_MASTER_CLK>;
116 + clock-names = "core";
120 + status = "disabled";
123 + compatible = "snps,dwc3";
124 + reg = <0x11000000 0xcd00>;
125 + interrupts = <0 110 0x4>;
126 + usb-phy = <&hs_phy_0>, <&ss_phy_0>;
127 + phy-names = "usb2-phy", "usb3-phy";
134 + compatible = "qcom,dwc3";
135 + #address-cells = <1>;
137 + clocks = <&gcc USB30_1_MASTER_CLK>;
138 + clock-names = "core";
142 + status = "disabled";
145 + compatible = "snps,dwc3";
146 + reg = <0x10000000 0xcd00>;
147 + interrupts = <0 205 0x4>;
148 + usb-phy = <&hs_phy_1>, <&ss_phy_1>;
149 + phy-names = "usb2-phy", "usb3-phy";