1 From 8a51ac2a4e36505e1ff82b0e49fd8b2edd0b7695 Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Wed, 18 Jun 2014 14:15:58 -0700
4 Subject: [PATCH 166/182] clk: qcom: Add support for High-Frequency PLLs
7 HFPLLs are the main frequency source for Krait CPU clocks. Add
8 support for changing the rate of these PLLs.
10 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
12 drivers/clk/qcom/Makefile | 1 +
13 drivers/clk/qcom/clk-hfpll.c | 260 ++++++++++++++++++++++++++++++++++++++++++
14 drivers/clk/qcom/clk-hfpll.h | 54 +++++++++
15 3 files changed, 315 insertions(+)
16 create mode 100644 drivers/clk/qcom/clk-hfpll.c
17 create mode 100644 drivers/clk/qcom/clk-hfpll.h
19 --- a/drivers/clk/qcom/Makefile
20 +++ b/drivers/clk/qcom/Makefile
21 @@ -7,6 +7,7 @@ clk-qcom-y += clk-rcg.o
22 clk-qcom-y += clk-rcg2.o
23 clk-qcom-y += clk-branch.o
24 clk-qcom-y += clk-generic.o
25 +clk-qcom-y += clk-hfpll.o
28 obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o
30 +++ b/drivers/clk/qcom/clk-hfpll.c
33 + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
35 + * This program is free software; you can redistribute it and/or modify
36 + * it under the terms of the GNU General Public License version 2 and
37 + * only version 2 as published by the Free Software Foundation.
39 + * This program is distributed in the hope that it will be useful,
40 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
41 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
42 + * GNU General Public License for more details.
44 +#include <linux/kernel.h>
45 +#include <linux/module.h>
46 +#include <linux/init.h>
47 +#include <linux/regmap.h>
48 +#include <linux/delay.h>
49 +#include <linux/err.h>
50 +#include <linux/clk-provider.h>
51 +#include <linux/spinlock.h>
53 +#include "clk-regmap.h"
54 +#include "clk-hfpll.h"
56 +#define PLL_OUTCTRL BIT(0)
57 +#define PLL_BYPASSNL BIT(1)
58 +#define PLL_RESET_N BIT(2)
60 +/* Initialize a HFPLL at a given rate and enable it. */
61 +static void __clk_hfpll_init_once(struct clk_hw *hw)
63 + struct clk_hfpll *h = to_clk_hfpll(hw);
64 + struct hfpll_data const *hd = h->d;
65 + struct regmap *regmap = h->clkr.regmap;
67 + if (likely(h->init_done))
70 + /* Configure PLL parameters for integer mode. */
72 + regmap_write(regmap, hd->config_reg, hd->config_val);
73 + regmap_write(regmap, hd->m_reg, 0);
74 + regmap_write(regmap, hd->n_reg, 1);
77 + u32 regval = hd->user_val;
80 + rate = __clk_get_rate(hw->clk);
82 + /* Pick the right VCO. */
83 + if (hd->user_vco_mask && rate > hd->low_vco_max_rate)
84 + regval |= hd->user_vco_mask;
85 + regmap_write(regmap, hd->user_reg, regval);
89 + regmap_write(regmap, hd->droop_reg, hd->droop_val);
91 + h->init_done = true;
94 +static void __clk_hfpll_enable(struct clk_hw *hw)
96 + struct clk_hfpll *h = to_clk_hfpll(hw);
97 + struct hfpll_data const *hd = h->d;
98 + struct regmap *regmap = h->clkr.regmap;
101 + __clk_hfpll_init_once(hw);
103 + /* Disable PLL bypass mode. */
104 + regmap_update_bits(regmap, hd->mode_reg, PLL_BYPASSNL, PLL_BYPASSNL);
107 + * H/W requires a 5us delay between disabling the bypass and
108 + * de-asserting the reset. Delay 10us just to be safe.
113 + /* De-assert active-low PLL reset. */
114 + regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
116 + /* Wait for PLL to lock. */
117 + if (hd->status_reg) {
119 + regmap_read(regmap, hd->status_reg, &val);
120 + } while (!(val & BIT(hd->lock_bit)));
126 + /* Enable PLL output. */
127 + regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL);
129 + /* Make sure the enable is done before returning. */
133 +/* Enable an already-configured HFPLL. */
134 +static int clk_hfpll_enable(struct clk_hw *hw)
136 + unsigned long flags;
137 + struct clk_hfpll *h = to_clk_hfpll(hw);
138 + struct hfpll_data const *hd = h->d;
139 + struct regmap *regmap = h->clkr.regmap;
142 + spin_lock_irqsave(&h->lock, flags);
143 + regmap_read(regmap, hd->mode_reg, &mode);
144 + if (!(mode & (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)))
145 + __clk_hfpll_enable(hw);
146 + spin_unlock_irqrestore(&h->lock, flags);
151 +static void __clk_hfpll_disable(struct clk_hw *hw)
153 + struct clk_hfpll *h = to_clk_hfpll(hw);
154 + struct hfpll_data const *hd = h->d;
155 + struct regmap *regmap = h->clkr.regmap;
158 + * Disable the PLL output, disable test mode, enable the bypass mode,
159 + * and assert the reset.
161 + regmap_update_bits(regmap, hd->mode_reg,
162 + PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL, 0);
165 +static void clk_hfpll_disable(struct clk_hw *hw)
167 + struct clk_hfpll *h = to_clk_hfpll(hw);
168 + unsigned long flags;
170 + spin_lock_irqsave(&h->lock, flags);
171 + __clk_hfpll_disable(hw);
172 + spin_unlock_irqrestore(&h->lock, flags);
175 +static long clk_hfpll_round_rate(struct clk_hw *hw, unsigned long rate,
176 + unsigned long *parent_rate)
178 + struct clk_hfpll *h = to_clk_hfpll(hw);
179 + struct hfpll_data const *hd = h->d;
180 + unsigned long rrate;
182 + rate = clamp(rate, hd->min_rate, hd->max_rate);
184 + rrate = DIV_ROUND_UP(rate, *parent_rate) * *parent_rate;
185 + if (rrate > hd->max_rate)
186 + rrate -= *parent_rate;
192 + * For optimization reasons, assumes no downstream clocks are actively using
195 +static int clk_hfpll_set_rate(struct clk_hw *hw, unsigned long rate,
196 + unsigned long parent_rate)
198 + struct clk_hfpll *h = to_clk_hfpll(hw);
199 + struct hfpll_data const *hd = h->d;
200 + struct regmap *regmap = h->clkr.regmap;
201 + unsigned long flags;
205 + l_val = rate / parent_rate;
207 + spin_lock_irqsave(&h->lock, flags);
209 + enabled = __clk_is_enabled(hw->clk);
211 + __clk_hfpll_disable(hw);
213 + /* Pick the right VCO. */
214 + if (hd->user_reg && hd->user_vco_mask) {
215 + regmap_read(regmap, hd->user_reg, &val);
216 + if (rate <= hd->low_vco_max_rate)
217 + val &= ~hd->user_vco_mask;
219 + val |= hd->user_vco_mask;
220 + regmap_write(regmap, hd->user_reg, val);
223 + regmap_write(regmap, hd->l_reg, l_val);
226 + __clk_hfpll_enable(hw);
228 + spin_unlock_irqrestore(&h->lock, flags);
233 +static unsigned long clk_hfpll_recalc_rate(struct clk_hw *hw,
234 + unsigned long parent_rate)
236 + struct clk_hfpll *h = to_clk_hfpll(hw);
237 + struct hfpll_data const *hd = h->d;
238 + struct regmap *regmap = h->clkr.regmap;
241 + regmap_read(regmap, hd->l_reg, &l_val);
243 + return l_val * parent_rate;
246 +static void clk_hfpll_init(struct clk_hw *hw)
248 + struct clk_hfpll *h = to_clk_hfpll(hw);
249 + struct hfpll_data const *hd = h->d;
250 + struct regmap *regmap = h->clkr.regmap;
253 + regmap_read(regmap, hd->mode_reg, &mode);
254 + if (mode != (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL)) {
255 + __clk_hfpll_init_once(hw);
259 + if (hd->status_reg) {
260 + regmap_read(regmap, hd->status_reg, &status);
261 + if (!(status & BIT(hd->lock_bit))) {
262 + WARN(1, "HFPLL %s is ON, but not locked!\n",
263 + __clk_get_name(hw->clk));
264 + clk_hfpll_disable(hw);
265 + __clk_hfpll_init_once(hw);
270 +static int hfpll_is_enabled(struct clk_hw *hw)
272 + struct clk_hfpll *h = to_clk_hfpll(hw);
273 + struct hfpll_data const *hd = h->d;
274 + struct regmap *regmap = h->clkr.regmap;
277 + regmap_read(regmap, hd->mode_reg, &mode);
279 + return mode == (PLL_BYPASSNL | PLL_RESET_N | PLL_OUTCTRL);
282 +const struct clk_ops clk_ops_hfpll = {
283 + .enable = clk_hfpll_enable,
284 + .disable = clk_hfpll_disable,
285 + .is_enabled = hfpll_is_enabled,
286 + .round_rate = clk_hfpll_round_rate,
287 + .set_rate = clk_hfpll_set_rate,
288 + .recalc_rate = clk_hfpll_recalc_rate,
289 + .init = clk_hfpll_init,
291 +EXPORT_SYMBOL_GPL(clk_ops_hfpll);
293 +++ b/drivers/clk/qcom/clk-hfpll.h
296 + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
298 + * This program is free software; you can redistribute it and/or modify
299 + * it under the terms of the GNU General Public License version 2 and
300 + * only version 2 as published by the Free Software Foundation.
302 + * This program is distributed in the hope that it will be useful,
303 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
304 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
305 + * GNU General Public License for more details.
307 +#ifndef __QCOM_CLK_HFPLL_H__
308 +#define __QCOM_CLK_HFPLL_H__
310 +#include <linux/clk-provider.h>
311 +#include <linux/spinlock.h>
312 +#include "clk-regmap.h"
329 + unsigned long low_vco_max_rate;
331 + unsigned long min_rate;
332 + unsigned long max_rate;
336 + struct hfpll_data const *d;
339 + struct clk_regmap clkr;
343 +#define to_clk_hfpll(_hw) \
344 + container_of(to_clk_regmap(_hw), struct clk_hfpll, clkr)
346 +extern const struct clk_ops clk_ops_hfpll;