ipq806x: Add support for IPQ806x chip family
[openwrt/staging/dangole.git] / target / linux / ipq806x / patches / 0167-clk-qcom-Add-HFPLL-driver.patch
1 From 49134da893bc11e833e3d87139c57e3b84e65219 Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Thu, 19 Jun 2014 18:46:31 -0700
4 Subject: [PATCH 167/182] clk: qcom: Add HFPLL driver
5
6 On some devices (MSM8974 for example), the HFPLLs are
7 instantiated within the Krait processor subsystem as separate
8 register regions. Add a driver for these PLLs so that we can
9 provide HFPLL clocks for use by the system.
10
11 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
12 ---
13 drivers/clk/qcom/Kconfig | 8 ++++
14 drivers/clk/qcom/Makefile | 1 +
15 drivers/clk/qcom/hfpll.c | 110 +++++++++++++++++++++++++++++++++++++++++++++
16 3 files changed, 119 insertions(+)
17 create mode 100644 drivers/clk/qcom/hfpll.c
18
19 diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
20 index cfaa54c..de8ba31 100644
21 --- a/drivers/clk/qcom/Kconfig
22 +++ b/drivers/clk/qcom/Kconfig
23 @@ -53,3 +53,11 @@ config MSM_MMCC_8974
24 Support for the multimedia clock controller on msm8974 devices.
25 Say Y if you want to support multimedia devices such as display,
26 graphics, video encode/decode, camera, etc.
27 +
28 +config QCOM_HFPLL
29 + tristate "High-Frequency PLL (HFPLL) Clock Controller"
30 + depends on COMMON_CLK_QCOM
31 + help
32 + Support for the high-frequency PLLs present on Qualcomm devices.
33 + Say Y if you want to support CPU frequency scaling on devices
34 + such as MSM8974, APQ8084, etc.
35 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
36 index 93fd03f..d0d8e3d 100644
37 --- a/drivers/clk/qcom/Makefile
38 +++ b/drivers/clk/qcom/Makefile
39 @@ -16,3 +16,4 @@ obj-$(CONFIG_MSM_GCC_8960) += gcc-msm8960.o
40 obj-$(CONFIG_MSM_GCC_8974) += gcc-msm8974.o
41 obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
42 obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
43 +obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
44 diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
45 new file mode 100644
46 index 0000000..701a377
47 --- /dev/null
48 +++ b/drivers/clk/qcom/hfpll.c
49 @@ -0,0 +1,110 @@
50 +/*
51 + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
52 + *
53 + * This program is free software; you can redistribute it and/or modify
54 + * it under the terms of the GNU General Public License version 2 and
55 + * only version 2 as published by the Free Software Foundation.
56 + *
57 + * This program is distributed in the hope that it will be useful,
58 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
59 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
60 + * GNU General Public License for more details.
61 + */
62 +
63 +#include <linux/kernel.h>
64 +#include <linux/init.h>
65 +#include <linux/module.h>
66 +#include <linux/platform_device.h>
67 +#include <linux/of.h>
68 +#include <linux/clk.h>
69 +#include <linux/clk-provider.h>
70 +#include <linux/regmap.h>
71 +
72 +#include "clk-regmap.h"
73 +#include "clk-hfpll.h"
74 +
75 +static const struct hfpll_data hdata = {
76 + .mode_reg = 0x00,
77 + .l_reg = 0x04,
78 + .m_reg = 0x08,
79 + .n_reg = 0x0c,
80 + .user_reg = 0x10,
81 + .config_reg = 0x14,
82 + .config_val = 0x430405d,
83 + .status_reg = 0x1c,
84 + .lock_bit = 16,
85 +
86 + .user_val = 0x8,
87 + .user_vco_mask = 0x100000,
88 + .low_vco_max_rate = 1248000000,
89 + .min_rate = 537600000UL,
90 + .max_rate = 2900000000UL,
91 +};
92 +
93 +static const struct of_device_id qcom_hfpll_match_table[] = {
94 + { .compatible = "qcom,hfpll" },
95 + { }
96 +};
97 +MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
98 +
99 +static struct regmap_config hfpll_regmap_config = {
100 + .reg_bits = 32,
101 + .reg_stride = 4,
102 + .val_bits = 32,
103 + .max_register = 0x30,
104 + .fast_io = true,
105 +};
106 +
107 +static int qcom_hfpll_probe(struct platform_device *pdev)
108 +{
109 + struct clk *clk;
110 + struct resource *res;
111 + struct device *dev = &pdev->dev;
112 + void __iomem *base;
113 + struct regmap *regmap;
114 + struct clk_hfpll *h;
115 + struct clk_init_data init = {
116 + .parent_names = (const char *[]){ "xo" },
117 + .num_parents = 1,
118 + .ops = &clk_ops_hfpll,
119 + };
120 +
121 + h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
122 + if (!h)
123 + return -ENOMEM;
124 +
125 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
126 + base = devm_ioremap_resource(dev, res);
127 + if (IS_ERR(base))
128 + return PTR_ERR(base);
129 +
130 + regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config);
131 + if (IS_ERR(regmap))
132 + return PTR_ERR(regmap);
133 +
134 + if (of_property_read_string_index(dev->of_node, "clock-output-names",
135 + 0, &init.name))
136 + return -ENODEV;
137 +
138 + h->d = &hdata;
139 + h->clkr.hw.init = &init;
140 + spin_lock_init(&h->lock);
141 +
142 + clk = devm_clk_register_regmap(&pdev->dev, &h->clkr);
143 +
144 + return PTR_ERR_OR_ZERO(clk);
145 +}
146 +
147 +static struct platform_driver qcom_hfpll_driver = {
148 + .probe = qcom_hfpll_probe,
149 + .driver = {
150 + .name = "qcom-hfpll",
151 + .owner = THIS_MODULE,
152 + .of_match_table = qcom_hfpll_match_table,
153 + },
154 +};
155 +module_platform_driver(qcom_hfpll_driver);
156 +
157 +MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
158 +MODULE_LICENSE("GPL v2");
159 +MODULE_ALIAS("platform:qcom-hfpll");
160 --
161 1.7.10.4
162