1 From 6912e27d97ba5671e8c2434bed0ebd23fde5e13d Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Wed, 18 Jun 2014 14:29:29 -0700
4 Subject: [PATCH 171/182] clk: qcom: Add Krait clock controller driver
6 The Krait CPU clocks are made up of a primary mux and secondary
7 mux for each CPU and the L2, controlled via cp15 accessors. For
8 Kraits within KPSSv1 each secondary mux accepts a different aux
9 source, but on KPSSv2 each secondary mux accepts the same aux
12 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
14 drivers/clk/qcom/Kconfig | 8 +
15 drivers/clk/qcom/Makefile | 1 +
16 drivers/clk/qcom/krait-cc.c | 364 +++++++++++++++++++++++++++++++++++++++++++
17 3 files changed, 373 insertions(+)
18 create mode 100644 drivers/clk/qcom/krait-cc.c
20 --- a/drivers/clk/qcom/Kconfig
21 +++ b/drivers/clk/qcom/Kconfig
22 @@ -70,6 +70,14 @@ config KPSS_XCC
23 if you want to support CPU frequency scaling on devices such
24 as MSM8960, APQ8064, etc.
27 + tristate "Krait Clock Controller"
28 + depends on COMMON_CLK_QCOM && ARM
31 + Support for the Krait CPU clocks on Qualcomm devices.
32 + Say Y if you want to support CPU frequency scaling.
36 select KRAIT_L2_ACCESSORS
37 --- a/drivers/clk/qcom/Makefile
38 +++ b/drivers/clk/qcom/Makefile
39 @@ -19,3 +19,4 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8
40 obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
41 obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
42 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
43 +obj-$(CONFIG_KRAITCC) += krait-cc.o
45 +++ b/drivers/clk/qcom/krait-cc.c
47 +/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
49 + * This program is free software; you can redistribute it and/or modify
50 + * it under the terms of the GNU General Public License version 2 and
51 + * only version 2 as published by the Free Software Foundation.
53 + * This program is distributed in the hope that it will be useful,
54 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
55 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
56 + * GNU General Public License for more details.
59 +#include <linux/kernel.h>
60 +#include <linux/init.h>
61 +#include <linux/module.h>
62 +#include <linux/platform_device.h>
63 +#include <linux/err.h>
64 +#include <linux/io.h>
65 +#include <linux/of.h>
66 +#include <linux/of_device.h>
67 +#include <linux/clk.h>
68 +#include <linux/clk-provider.h>
69 +#include <linux/slab.h>
71 +#include <asm/smp_plat.h>
73 +#include "clk-krait.h"
75 +DEFINE_FIXED_DIV_CLK(acpu_aux, 2, "gpll0_vote");
77 +static u8 sec_mux_map[] = {
82 +static u8 pri_mux_map[] = {
89 +krait_add_div(struct device *dev, int id, const char *s, unsigned offset)
91 + struct div_clk *div;
92 + struct clk_init_data init = {
94 + .ops = &clk_ops_div,
95 + .flags = CLK_SET_RATE_PARENT,
97 + const char *p_names[1];
100 + div = devm_kzalloc(dev, sizeof(*dev), GFP_KERNEL);
105 + div->data.min_div = 2;
106 + div->data.max_div = 2;
107 + div->ops = &clk_div_ops_kpss_div2;
110 + div->priv = (void *)(id >= 0);
111 + div->offset = offset;
112 + div->hw.init = &init;
114 + init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
118 + init.parent_names = p_names;
119 + p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
125 + clk = devm_clk_register(dev, &div->hw);
129 + return PTR_ERR_OR_ZERO(clk);
133 +krait_add_sec_mux(struct device *dev, int id, const char *s, unsigned offset,
136 + struct mux_clk *mux;
137 + static const char *sec_mux_list[] = {
141 + struct clk_init_data init = {
142 + .parent_names = sec_mux_list,
143 + .num_parents = ARRAY_SIZE(sec_mux_list),
144 + .ops = &clk_ops_gen_mux,
145 + .flags = CLK_SET_RATE_PARENT,
149 + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
153 + mux->offset = offset;
154 + mux->priv = (void *)(id >= 0);
155 + mux->has_safe_parent = true;
157 + mux->ops = &clk_mux_ops_kpss;
160 + mux->parent_map = sec_mux_map;
161 + mux->hw.init = &init;
163 + init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
168 + sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
169 + if (!sec_mux_list[0]) {
170 + clk = ERR_PTR(-ENOMEM);
175 + clk = devm_clk_register(dev, &mux->hw);
178 + kfree(sec_mux_list[0]);
181 + return PTR_ERR_OR_ZERO(clk);
185 +krait_add_pri_mux(struct device *dev, int id, const char * s, unsigned offset)
187 + struct mux_clk *mux;
188 + const char *p_names[3];
189 + struct clk_init_data init = {
190 + .parent_names = p_names,
191 + .num_parents = ARRAY_SIZE(p_names),
192 + .ops = &clk_ops_gen_mux,
193 + .flags = CLK_SET_RATE_PARENT,
197 + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
199 + return ERR_PTR(-ENOMEM);
201 + mux->has_safe_parent = true;
203 + mux->ops = &clk_mux_ops_kpss;
206 + mux->offset = offset;
207 + mux->priv = (void *)(id >= 0);
208 + mux->parent_map = pri_mux_map;
209 + mux->hw.init = &init;
211 + init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
213 + return ERR_PTR(-ENOMEM);
215 + p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
217 + clk = ERR_PTR(-ENOMEM);
221 + p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
223 + clk = ERR_PTR(-ENOMEM);
227 + p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
229 + clk = ERR_PTR(-ENOMEM);
233 + clk = devm_clk_register(dev, &mux->hw);
245 +/* id < 0 for L2, otherwise id == physical CPU number */
246 +static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
255 + offset = 0x4501 + (0x1000 * id);
256 + s = p = kasprintf(GFP_KERNEL, "%d", id);
258 + return ERR_PTR(-ENOMEM);
264 + ret = krait_add_div(dev, id, s, offset);
266 + clk = ERR_PTR(ret);
270 + ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
272 + clk = ERR_PTR(ret);
276 + clk = krait_add_pri_mux(dev, id, s, offset);
282 +static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
284 + unsigned int idx = clkspec->args[0];
285 + struct clk **clks = data;
288 + pr_err("%s: invalid clock index %d\n", __func__, idx);
289 + return ERR_PTR(-EINVAL);
292 + return clks[idx] ? : ERR_PTR(-ENODEV);
295 +static const struct of_device_id krait_cc_match_table[] = {
296 + { .compatible = "qcom,krait-cc-v1", (void *)1UL },
297 + { .compatible = "qcom,krait-cc-v2" },
300 +MODULE_DEVICE_TABLE(of, krait_cc_match_table);
302 +static int krait_cc_probe(struct platform_device *pdev)
304 + struct device *dev = &pdev->dev;
305 + const struct of_device_id *id;
306 + unsigned long cur_rate, aux_rate;
310 + struct clk *l2_pri_mux_clk;
312 + id = of_match_device(krait_cc_match_table, &pdev->dev);
316 + /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
317 + clk = clk_register_fixed_rate(dev, "qsb", NULL, CLK_IS_ROOT, 1);
319 + return PTR_ERR(clk);
322 + clk = devm_clk_register(dev, &acpu_aux.hw);
324 + return PTR_ERR(clk);
327 + /* Krait configurations have at most 4 CPUs and one L2 */
328 + clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
332 + for_each_possible_cpu(i) {
333 + cpu = cpu_logical_map(i);
334 + clk = krait_add_clks(dev, cpu, id->data);
336 + return PTR_ERR(clk);
340 + l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
341 + if (IS_ERR(l2_pri_mux_clk))
342 + return PTR_ERR(l2_pri_mux_clk);
343 + clks[4] = l2_pri_mux_clk;
346 + * We don't want the CPU or L2 clocks to be turned off at late init
347 + * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
348 + * refcount of these clocks. Any cpufreq/hotplug manager can assume
349 + * that the clocks have already been prepared and enabled by the time
352 + for_each_online_cpu(i) {
353 + cpu = cpu_logical_map(i);
354 + clk_prepare_enable(l2_pri_mux_clk);
355 + WARN(clk_prepare_enable(clks[cpu]),
356 + "Unable to turn on CPU%d clock", cpu);
360 + * Force reinit of HFPLLs and muxes to overwrite any potential
361 + * incorrect configuration of HFPLLs and muxes by the bootloader.
362 + * While at it, also make sure the cores are running at known rates
363 + * and print the current rate.
365 + * The clocks are set to aux clock rate first to make sure the
366 + * secondary mux is not sourcing off of QSB. The rate is then set to
367 + * two different rates to force a HFPLL reinit under all
370 + cur_rate = clk_get_rate(l2_pri_mux_clk);
371 + aux_rate = 384000000;
372 + if (cur_rate == 1) {
373 + pr_info("L2 @ QSB rate. Forcing new rate.\n");
374 + cur_rate = aux_rate;
376 + clk_set_rate(l2_pri_mux_clk, aux_rate);
377 + clk_set_rate(l2_pri_mux_clk, 2);
378 + clk_set_rate(l2_pri_mux_clk, cur_rate);
379 + pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
380 + for_each_possible_cpu(i) {
381 + cpu = cpu_logical_map(i);
383 + cur_rate = clk_get_rate(clk);
384 + if (cur_rate == 1) {
385 + pr_info("CPU%d @ QSB rate. Forcing new rate.\n", i);
386 + cur_rate = aux_rate;
388 + clk_set_rate(clk, aux_rate);
389 + clk_set_rate(clk, 2);
390 + clk_set_rate(clk, cur_rate);
391 + pr_info("CPU%d @ %lu KHz\n", i, clk_get_rate(clk) / 1000);
394 + of_clk_add_provider(dev->of_node, krait_of_get, clks);
399 +static struct platform_driver krait_cc_driver = {
400 + .probe = krait_cc_probe,
402 + .name = "clock-krait",
403 + .of_match_table = krait_cc_match_table,
404 + .owner = THIS_MODULE,
407 +module_platform_driver(krait_cc_driver);
409 +MODULE_DESCRIPTION("Krait CPU Clock Driver");
410 +MODULE_LICENSE("GPL v2");