target/linux/ipq806x/patches/0171-clk-qcom-Add-Krait-clock-controller-driver.patch

   1 From 6912e27d97ba5671e8c2434bed0ebd23fde5e13d Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Wed, 18 Jun 2014 14:29:29 -0700
   4 Subject: [PATCH 171/182] clk: qcom: Add Krait clock controller driver
   5
   6 The Krait CPU clocks are made up of a primary mux and secondary
   7 mux for each CPU and the L2, controlled via cp15 accessors. For
   8 Kraits within KPSSv1 each secondary mux accepts a different aux
   9 source, but on KPSSv2 each secondary mux accepts the same aux
  10 source.
  11
  12 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
  13 ---
  14  drivers/clk/qcom/Kconfig    |    8 +
  15  drivers/clk/qcom/Makefile   |    1 +
  16  drivers/clk/qcom/krait-cc.c |  364 +++++++++++++++++++++++++++++++++++++++++++
  17  3 files changed, 373 insertions(+)
  18  create mode 100644 drivers/clk/qcom/krait-cc.c
  19
  20 diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
  21 index e9e5360..7418108 100644
  22 --- a/drivers/clk/qcom/Kconfig
  23 +++ b/drivers/clk/qcom/Kconfig
  24 @@ -70,6 +70,14 @@ config KPSS_XCC
  25           if you want to support CPU frequency scaling on devices such
  26           as MSM8960, APQ8064, etc.
  27
  28 +config KRAITCC
  29 +       tristate "Krait Clock Controller"
  30 +       depends on COMMON_CLK_QCOM && ARM
  31 +       select KRAIT_CLOCKS
  32 +       help
  33 +         Support for the Krait CPU clocks on Qualcomm devices.
  34 +         Say Y if you want to support CPU frequency scaling.
  35 +
  36  config KRAIT_CLOCKS
  37         bool
  38         select KRAIT_L2_ACCESSORS
  39 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
  40 index 29b2a45..1b88abe 100644
  41 --- a/drivers/clk/qcom/Makefile
  42 +++ b/drivers/clk/qcom/Makefile
  43 @@ -19,3 +19,4 @@ obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
  44  obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
  45  obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
  46  obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
  47 +obj-$(CONFIG_KRAITCC) += krait-cc.o
  48 diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
  49 new file mode 100644
  50 index 0000000..90985ea
  51 --- /dev/null
  52 +++ b/drivers/clk/qcom/krait-cc.c
  53 @@ -0,0 +1,364 @@
  54 +/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
  55 + *
  56 + * This program is free software; you can redistribute it and/or modify
  57 + * it under the terms of the GNU General Public License version 2 and
  58 + * only version 2 as published by the Free Software Foundation.
  59 + *
  60 + * This program is distributed in the hope that it will be useful,
  61 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  62 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  63 + * GNU General Public License for more details.
  64 + */
  65 +
  66 +#include <linux/kernel.h>
  67 +#include <linux/init.h>
  68 +#include <linux/module.h>
  69 +#include <linux/platform_device.h>
  70 +#include <linux/err.h>
  71 +#include <linux/io.h>
  72 +#include <linux/of.h>
  73 +#include <linux/of_device.h>
  74 +#include <linux/clk.h>
  75 +#include <linux/clk-provider.h>
  76 +#include <linux/slab.h>
  77 +
  78 +#include <asm/smp_plat.h>
  79 +
  80 +#include "clk-krait.h"
  81 +
  82 +DEFINE_FIXED_DIV_CLK(acpu_aux, 2, "gpll0_vote");
  83 +
  84 +static u8 sec_mux_map[] = {
  85 +       2,
  86 +       0,
  87 +};
  88 +
  89 +static u8 pri_mux_map[] = {
  90 +       1,
  91 +       2,
  92 +       0,
  93 +};
  94 +
  95 +static int
  96 +krait_add_div(struct device *dev, int id, const char *s, unsigned offset)
  97 +{
  98 +       struct div_clk *div;
  99 +       struct clk_init_data init = {
 100 +               .num_parents = 1,
 101 +               .ops = &clk_ops_div,
 102 +               .flags = CLK_SET_RATE_PARENT,
 103 +       };
 104 +       const char *p_names[1];
 105 +       struct clk *clk;
 106 +
 107 +       div = devm_kzalloc(dev, sizeof(*dev), GFP_KERNEL);
 108 +       if (!div)
 109 +               return -ENOMEM;
 110 +
 111 +       div->data.div = 2;
 112 +       div->data.min_div = 2;
 113 +       div->data.max_div = 2;
 114 +       div->ops = &clk_div_ops_kpss_div2;
 115 +       div->mask = 0x3;
 116 +       div->shift = 6;
 117 +       div->priv = (void *)(id >= 0);
 118 +       div->offset = offset;
 119 +       div->hw.init = &init;
 120 +
 121 +       init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
 122 +       if (!init.name)
 123 +               return -ENOMEM;
 124 +
 125 +       init.parent_names = p_names;
 126 +       p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
 127 +       if (!p_names[0]) {
 128 +               kfree(init.name);
 129 +               return -ENOMEM;
 130 +       }
 131 +
 132 +       clk = devm_clk_register(dev, &div->hw);
 133 +       kfree(p_names[0]);
 134 +       kfree(init.name);
 135 +
 136 +       return PTR_ERR_OR_ZERO(clk);
 137 +}
 138 +
 139 +static int
 140 +krait_add_sec_mux(struct device *dev, int id, const char *s, unsigned offset,
 141 +                 bool unique_aux)
 142 +{
 143 +       struct mux_clk *mux;
 144 +       static const char *sec_mux_list[] = {
 145 +               "acpu_aux",
 146 +               "qsb",
 147 +       };
 148 +       struct clk_init_data init = {
 149 +               .parent_names = sec_mux_list,
 150 +               .num_parents = ARRAY_SIZE(sec_mux_list),
 151 +               .ops = &clk_ops_gen_mux,
 152 +               .flags = CLK_SET_RATE_PARENT,
 153 +       };
 154 +       struct clk *clk;
 155 +
 156 +       mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
 157 +       if (!mux)
 158 +               return -ENOMEM;
 159 +
 160 +       mux->offset = offset;
 161 +       mux->priv = (void *)(id >= 0);
 162 +       mux->has_safe_parent = true;
 163 +       mux->safe_sel = 2;
 164 +       mux->ops = &clk_mux_ops_kpss;
 165 +       mux->mask = 0x3;
 166 +       mux->shift = 2;
 167 +       mux->parent_map = sec_mux_map;
 168 +       mux->hw.init = &init;
 169 +
 170 +       init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
 171 +       if (!init.name)
 172 +               return -ENOMEM;
 173 +
 174 +       if (unique_aux) {
 175 +               sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
 176 +               if (!sec_mux_list[0]) {
 177 +                       clk = ERR_PTR(-ENOMEM);
 178 +                       goto err_aux;
 179 +               }
 180 +       }
 181 +
 182 +       clk = devm_clk_register(dev, &mux->hw);
 183 +
 184 +       if (unique_aux)
 185 +               kfree(sec_mux_list[0]);
 186 +err_aux:
 187 +       kfree(init.name);
 188 +       return PTR_ERR_OR_ZERO(clk);
 189 +}
 190 +
 191 +static struct clk *
 192 +krait_add_pri_mux(struct device *dev, int id, const char * s, unsigned offset)
 193 +{
 194 +       struct mux_clk *mux;
 195 +       const char *p_names[3];
 196 +       struct clk_init_data init = {
 197 +               .parent_names = p_names,
 198 +               .num_parents = ARRAY_SIZE(p_names),
 199 +               .ops = &clk_ops_gen_mux,
 200 +               .flags = CLK_SET_RATE_PARENT,
 201 +       };
 202 +       struct clk *clk;
 203 +
 204 +       mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
 205 +       if (!mux)
 206 +               return ERR_PTR(-ENOMEM);
 207 +
 208 +       mux->has_safe_parent = true;
 209 +       mux->safe_sel = 0;
 210 +       mux->ops = &clk_mux_ops_kpss;
 211 +       mux->mask = 0x3;
 212 +       mux->shift = 0;
 213 +       mux->offset = offset;
 214 +       mux->priv = (void *)(id >= 0);
 215 +       mux->parent_map = pri_mux_map;
 216 +       mux->hw.init = &init;
 217 +
 218 +       init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
 219 +       if (!init.name)
 220 +               return ERR_PTR(-ENOMEM);
 221 +
 222 +       p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
 223 +       if (!p_names[0]) {
 224 +               clk = ERR_PTR(-ENOMEM);
 225 +               goto err_p0;
 226 +       }
 227 +
 228 +       p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
 229 +       if (!p_names[1]) {
 230 +               clk = ERR_PTR(-ENOMEM);
 231 +               goto err_p1;
 232 +       }
 233 +
 234 +       p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
 235 +       if (!p_names[2]) {
 236 +               clk = ERR_PTR(-ENOMEM);
 237 +               goto err_p2;
 238 +       }
 239 +
 240 +       clk = devm_clk_register(dev, &mux->hw);
 241 +
 242 +       kfree(p_names[2]);
 243 +err_p2:
 244 +       kfree(p_names[1]);
 245 +err_p1:
 246 +       kfree(p_names[0]);
 247 +err_p0:
 248 +       kfree(init.name);
 249 +       return clk;
 250 +}
 251 +
 252 +/* id < 0 for L2, otherwise id == physical CPU number */
 253 +static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
 254 +{
 255 +       int ret;
 256 +       unsigned offset;
 257 +       void *p = NULL;
 258 +       const char *s;
 259 +       struct clk *clk;
 260 +
 261 +       if (id >= 0) {
 262 +               offset = 0x4501 + (0x1000 * id);
 263 +               s = p = kasprintf(GFP_KERNEL, "%d", id);
 264 +               if (!s)
 265 +                       return ERR_PTR(-ENOMEM);
 266 +       } else {
 267 +               offset = 0x500;
 268 +               s = "_l2";
 269 +       }
 270 +
 271 +       ret = krait_add_div(dev, id, s, offset);
 272 +       if (ret) {
 273 +               clk = ERR_PTR(ret);
 274 +               goto err;
 275 +       }
 276 +
 277 +       ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
 278 +       if (ret) {
 279 +               clk = ERR_PTR(ret);
 280 +               goto err;
 281 +       }
 282 +
 283 +       clk = krait_add_pri_mux(dev, id, s, offset);
 284 +err:
 285 +       kfree(p);
 286 +       return clk;
 287 +}
 288 +
 289 +static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
 290 +{
 291 +       unsigned int idx = clkspec->args[0];
 292 +       struct clk **clks = data;
 293 +
 294 +       if (idx >= 5) {
 295 +               pr_err("%s: invalid clock index %d\n", __func__, idx);
 296 +               return ERR_PTR(-EINVAL);
 297 +       }
 298 +
 299 +       return clks[idx] ? : ERR_PTR(-ENODEV);
 300 +}
 301 +
 302 +static const struct of_device_id krait_cc_match_table[] = {
 303 +       { .compatible = "qcom,krait-cc-v1", (void *)1UL },
 304 +       { .compatible = "qcom,krait-cc-v2" },
 305 +       {}
 306 +};
 307 +MODULE_DEVICE_TABLE(of, krait_cc_match_table);
 308 +
 309 +static int krait_cc_probe(struct platform_device *pdev)
 310 +{
 311 +       struct device *dev = &pdev->dev;
 312 +       const struct of_device_id *id;
 313 +       unsigned long cur_rate, aux_rate;
 314 +       int i, cpu;
 315 +       struct clk *clk;
 316 +       struct clk **clks;
 317 +       struct clk *l2_pri_mux_clk;
 318 +
 319 +       id = of_match_device(krait_cc_match_table, &pdev->dev);
 320 +       if (!id)
 321 +               return -ENODEV;
 322 +
 323 +       /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
 324 +       clk = clk_register_fixed_rate(dev, "qsb", NULL, CLK_IS_ROOT, 1);
 325 +       if (IS_ERR(clk))
 326 +               return PTR_ERR(clk);
 327 +
 328 +       if (!id->data) {
 329 +               clk = devm_clk_register(dev, &acpu_aux.hw);
 330 +               if (IS_ERR(clk))
 331 +                       return PTR_ERR(clk);
 332 +       }
 333 +
 334 +       /* Krait configurations have at most 4 CPUs and one L2 */
 335 +       clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
 336 +       if (!clks)
 337 +               return -ENOMEM;
 338 +
 339 +       for_each_possible_cpu(i) {
 340 +               cpu = cpu_logical_map(i);
 341 +               clk = krait_add_clks(dev, cpu, id->data);
 342 +               if (IS_ERR(clk))
 343 +                       return PTR_ERR(clk);
 344 +               clks[cpu] = clk;
 345 +       }
 346 +
 347 +       l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
 348 +       if (IS_ERR(l2_pri_mux_clk))
 349 +               return PTR_ERR(l2_pri_mux_clk);
 350 +       clks[4] = l2_pri_mux_clk;
 351 +
 352 +       /*
 353 +        * We don't want the CPU or L2 clocks to be turned off at late init
 354 +        * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
 355 +        * refcount of these clocks. Any cpufreq/hotplug manager can assume
 356 +        * that the clocks have already been prepared and enabled by the time
 357 +        * they take over.
 358 +        */
 359 +       for_each_online_cpu(i) {
 360 +               cpu = cpu_logical_map(i);
 361 +               clk_prepare_enable(l2_pri_mux_clk);
 362 +               WARN(clk_prepare_enable(clks[cpu]),
 363 +                       "Unable to turn on CPU%d clock", cpu);
 364 +       }
 365 +
 366 +       /*
 367 +        * Force reinit of HFPLLs and muxes to overwrite any potential
 368 +        * incorrect configuration of HFPLLs and muxes by the bootloader.
 369 +        * While at it, also make sure the cores are running at known rates
 370 +        * and print the current rate.
 371 +        *
 372 +        * The clocks are set to aux clock rate first to make sure the
 373 +        * secondary mux is not sourcing off of QSB. The rate is then set to
 374 +        * two different rates to force a HFPLL reinit under all
 375 +        * circumstances.
 376 +        */
 377 +       cur_rate = clk_get_rate(l2_pri_mux_clk);
 378 +       aux_rate = 384000000;
 379 +       if (cur_rate == 1) {
 380 +               pr_info("L2 @ QSB rate. Forcing new rate.\n");
 381 +               cur_rate = aux_rate;
 382 +       }
 383 +       clk_set_rate(l2_pri_mux_clk, aux_rate);
 384 +       clk_set_rate(l2_pri_mux_clk, 2);
 385 +       clk_set_rate(l2_pri_mux_clk, cur_rate);
 386 +       pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
 387 +       for_each_possible_cpu(i) {
 388 +               cpu = cpu_logical_map(i);
 389 +               clk = clks[cpu];
 390 +               cur_rate = clk_get_rate(clk);
 391 +               if (cur_rate == 1) {
 392 +                       pr_info("CPU%d @ QSB rate. Forcing new rate.\n", i);
 393 +                       cur_rate = aux_rate;
 394 +               }
 395 +               clk_set_rate(clk, aux_rate);
 396 +               clk_set_rate(clk, 2);
 397 +               clk_set_rate(clk, cur_rate);
 398 +               pr_info("CPU%d @ %lu KHz\n", i, clk_get_rate(clk) / 1000);
 399 +       }
 400 +
 401 +       of_clk_add_provider(dev->of_node, krait_of_get, clks);
 402 +
 403 +       return 0;
 404 +}
 405 +
 406 +static struct platform_driver krait_cc_driver = {
 407 +       .probe = krait_cc_probe,
 408 +       .driver = {
 409 +               .name = "clock-krait",
 410 +               .of_match_table = krait_cc_match_table,
 411 +               .owner = THIS_MODULE,
 412 +       },
 413 +};
 414 +module_platform_driver(krait_cc_driver);
 415 +
 416 +MODULE_DESCRIPTION("Krait CPU Clock Driver");
 417 +MODULE_LICENSE("GPL v2");
 418 --
 419 1.7.10.4
 420