1 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
2 +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
3 @@ -6,7 +6,8 @@ configuration settings. The mode settin
7 -- compatible: must contain "qcom,gsbi-v1.0.0" for APQ8064/IPQ8064
8 +- compatible: Should contain "qcom,gsbi-v1.0.0"
9 +- cell-index: Should contain the GSBI index
10 - reg: Address range for GSBI registers
11 - clocks: required clock
12 - clock-names: must contain "iface" entry
13 @@ -16,6 +17,8 @@ Required properties:
15 - qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
16 dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
17 +- syscon-tcsr: indicates phandle of TCSR syscon node. Required if child uses
20 Required properties if child node exists:
21 - #address-cells: Must be 1
22 @@ -39,6 +42,7 @@ Example for APQ8064:
25 compatible = "qcom,gsbi-v1.0.0";
27 reg = <0x16300000 0x100>;
28 clocks = <&gcc GSBI4_H_CLK>;
29 clock-names = "iface";
30 @@ -48,6 +52,8 @@ Example for APQ8064:
31 qcom,mode = <GSBI_PROT_I2C_UART>;
32 qcom,crci = <GSBI_CRCI_QUP>;
34 + syscon-tcsr = <&tcsr>;
36 /* child nodes go under here */
38 i2c_qup4: i2c@16380000 {
39 @@ -76,3 +82,9 @@ Example for APQ8064:
43 + tcsr: syscon@1a400000 {
44 + compatible = "qcom,apq8064-tcsr", "syscon";
45 + reg = <0x1a400000 0x100>;
49 --- a/drivers/soc/qcom/Kconfig
50 +++ b/drivers/soc/qcom/Kconfig
53 tristate "QCOM General Serial Bus Interface"
57 Say y here to enable GSBI support. The GSBI provides control
58 functions for connecting the underlying serial UART, SPI, and I2C
59 --- a/drivers/soc/qcom/qcom_gsbi.c
60 +++ b/drivers/soc/qcom/qcom_gsbi.c
63 #include <linux/of_platform.h>
64 #include <linux/platform_device.h>
65 +#include <linux/regmap.h>
66 +#include <linux/mfd/syscon.h>
67 +#include <dt-bindings/soc/qcom,gsbi.h>
69 #define GSBI_CTRL_REG 0x0000
70 #define GSBI_PROTOCOL_SHIFT 4
73 +#define TCSR_ADM_CRCI_BASE 0x70
77 + const u32 (*array)[MAX_GSBI];
80 +static const u32 crci_ipq8064[][MAX_GSBI] = {
82 + 0x000003, 0x00000c, 0x000030, 0x0000c0,
83 + 0x000300, 0x000c00, 0x003000, 0x00c000,
84 + 0x030000, 0x0c0000, 0x300000, 0xc00000
87 + 0x000003, 0x00000c, 0x000030, 0x0000c0,
88 + 0x000300, 0x000c00, 0x003000, 0x00c000,
89 + 0x030000, 0x0c0000, 0x300000, 0xc00000
93 +static const struct crci_config config_ipq8064 = {
94 + .num_rows = ARRAY_SIZE(crci_ipq8064),
95 + .array = crci_ipq8064,
98 +static const unsigned int crci_apq8064[][MAX_GSBI] = {
100 + 0x001800, 0x006000, 0x000030, 0x0000c0,
101 + 0x000300, 0x000400, 0x000000, 0x000000,
102 + 0x000000, 0x000000, 0x000000, 0x000000
105 + 0x000000, 0x000000, 0x000000, 0x000000,
106 + 0x000000, 0x000020, 0x0000c0, 0x000000,
107 + 0x000000, 0x000000, 0x000000, 0x000000
111 +static const struct crci_config config_apq8064 = {
112 + .num_rows = ARRAY_SIZE(crci_apq8064),
113 + .array = crci_apq8064,
116 +static const unsigned int crci_msm8960[][MAX_GSBI] = {
118 + 0x000003, 0x00000c, 0x000030, 0x0000c0,
119 + 0x000300, 0x000400, 0x000000, 0x000000,
120 + 0x000000, 0x000000, 0x000000, 0x000000
123 + 0x000000, 0x000000, 0x000000, 0x000000,
124 + 0x000000, 0x000020, 0x0000c0, 0x000300,
125 + 0x001800, 0x006000, 0x000000, 0x000000
129 +static const struct crci_config config_msm8960 = {
130 + .num_rows = ARRAY_SIZE(crci_msm8960),
131 + .array = crci_msm8960,
134 +static const unsigned int crci_msm8660[][MAX_GSBI] = {
136 + 0x000003, 0x00000c, 0x000030, 0x0000c0,
137 + 0x000300, 0x000c00, 0x003000, 0x00c000,
138 + 0x030000, 0x0c0000, 0x300000, 0xc00000
141 + 0x000003, 0x00000c, 0x000030, 0x0000c0,
142 + 0x000300, 0x000c00, 0x003000, 0x00c000,
143 + 0x030000, 0x0c0000, 0x300000, 0xc00000
146 + 0x000003, 0x00000c, 0x000030, 0x0000c0,
147 + 0x000300, 0x000c00, 0x003000, 0x00c000,
148 + 0x030000, 0x0c0000, 0x300000, 0xc00000
151 + 0x000003, 0x00000c, 0x000030, 0x0000c0,
152 + 0x000300, 0x000c00, 0x003000, 0x00c000,
153 + 0x030000, 0x0c0000, 0x300000, 0xc00000
157 +static const struct crci_config config_msm8660 = {
158 + .num_rows = ARRAY_SIZE(crci_msm8660),
159 + .array = crci_msm8660,
166 + struct regmap *tcsr;
169 +static const struct of_device_id tcsr_dt_match[] = {
170 + { .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064},
171 + { .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064},
172 + { .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960},
173 + { .compatible = "qcom,tcsr-msm8660", .data = &config_msm8660},
177 static int gsbi_probe(struct platform_device *pdev)
179 struct device_node *node = pdev->dev.of_node;
180 + struct device_node *tcsr_node;
181 + const struct of_device_id *match;
182 struct resource *res;
184 struct gsbi_info *gsbi;
186 + u32 mask, gsbi_num;
187 + const struct crci_config *config = NULL;
189 gsbi = devm_kzalloc(&pdev->dev, sizeof(*gsbi), GFP_KERNEL);
191 @@ -45,6 +152,32 @@ static int gsbi_probe(struct platform_de
193 return PTR_ERR(base);
195 + /* get the tcsr node and setup the config and regmap */
196 + gsbi->tcsr = syscon_regmap_lookup_by_phandle(node, "syscon-tcsr");
198 + if (!IS_ERR(gsbi->tcsr)) {
199 + tcsr_node = of_parse_phandle(node, "syscon-tcsr", 0);
201 + match = of_match_node(tcsr_dt_match, tcsr_node);
203 + config = match->data;
205 + dev_warn(&pdev->dev, "no matching TCSR\n");
207 + of_node_put(tcsr_node);
211 + if (of_property_read_u32(node, "cell-index", &gsbi_num)) {
212 + dev_err(&pdev->dev, "missing cell-index\n");
216 + if (gsbi_num < 1 || gsbi_num > MAX_GSBI) {
217 + dev_err(&pdev->dev, "invalid cell-index\n");
221 if (of_property_read_u32(node, "qcom,mode", &gsbi->mode)) {
222 dev_err(&pdev->dev, "missing mode configuration\n");
224 @@ -64,6 +197,25 @@ static int gsbi_probe(struct platform_de
225 writel_relaxed((gsbi->mode << GSBI_PROTOCOL_SHIFT) | gsbi->crci,
226 base + GSBI_CTRL_REG);
229 + * modify tcsr to reflect mode and ADM CRCI mux
230 + * Each gsbi contains a pair of bits, one for RX and one for TX
231 + * SPI mode requires both bits cleared, otherwise they are set
234 + for (i = 0; i < config->num_rows; i++) {
235 + mask = config->array[i][gsbi_num - 1];
237 + if (gsbi->mode == GSBI_PROT_SPI)
238 + regmap_update_bits(gsbi->tcsr,
239 + TCSR_ADM_CRCI_BASE + 4 * i, mask, 0);
241 + regmap_update_bits(gsbi->tcsr,
242 + TCSR_ADM_CRCI_BASE + 4 * i, mask, mask);
247 /* make sure the gsbi control write is not reordered */