1 --- a/drivers/pci/host/pcie-qcom.c
2 +++ b/drivers/pci/host/pcie-qcom.c
5 #include "pcie-designware.h"
8 +#define PCIE20_CAP 0x70
9 +#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10)
11 +#define PCIE20_AXI_MSTR_RESP_COMP_CTRL0 0x818
12 +#define PCIE20_AXI_MSTR_RESP_COMP_CTRL1 0x81c
14 +#define PCIE20_PLR_IATU_VIEWPORT 0x900
15 +#define PCIE20_PLR_IATU_REGION_OUTBOUND (0x0 << 31)
16 +#define PCIE20_PLR_IATU_REGION_INDEX(x) (x << 0)
18 +#define PCIE20_PLR_IATU_CTRL1 0x904
19 +#define PCIE20_PLR_IATU_TYPE_CFG0 (0x4 << 0)
20 +#define PCIE20_PLR_IATU_TYPE_MEM (0x0 << 0)
22 +#define PCIE20_PLR_IATU_CTRL2 0x908
23 +#define PCIE20_PLR_IATU_ENABLE BIT(31)
25 +#define PCIE20_PLR_IATU_LBAR 0x90C
26 +#define PCIE20_PLR_IATU_UBAR 0x910
27 +#define PCIE20_PLR_IATU_LAR 0x914
28 +#define PCIE20_PLR_IATU_LTAR 0x918
29 +#define PCIE20_PLR_IATU_UTAR 0x91c
31 +#define MSM_PCIE_DEV_CFG_ADDR 0x01000000
34 +#define PCIE20_PARF_PCS_DEEMPH 0x34
35 +#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) (x << 16)
36 +#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) (x << 8)
37 +#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) (x << 0)
39 +#define PCIE20_PARF_PCS_SWING 0x38
40 +#define PCS_SWING_TX_SWING_FULL(x) (x << 8)
41 +#define PCS_SWING_TX_SWING_LOW(x) (x << 0)
43 #define PCIE20_PARF_PHY_CTRL 0x40
44 +#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK (0x1f << 16)
45 +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) (x << 16)
47 #define PCIE20_PARF_PHY_REFCLK 0x4C
48 +#define REF_SSP_EN BIT(16)
49 +#define REF_USE_PAD BIT(12)
51 +#define PCIE20_PARF_CONFIG_BITS 0x50
52 +#define PHY_RX0_EQ(x) (x << 24)
54 #define PCIE20_PARF_DBI_BASE_ADDR 0x168
55 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c
56 #define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
58 #define PCIE20_ELBI_SYS_STTS 0x08
59 #define XMLH_LINK_UP BIT(10)
61 -#define PCIE20_CAP 0x70
62 -#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10)
64 #define PERST_DELAY_MIN_US 1000
65 #define PERST_DELAY_MAX_US 1005
67 @@ -56,14 +98,18 @@ struct qcom_pcie_resources_v0 {
68 struct clk *iface_clk;
71 + struct clk *aux_clk;
72 + struct clk *ref_clk;
73 struct reset_control *pci_reset;
74 struct reset_control *axi_reset;
75 struct reset_control *ahb_reset;
76 struct reset_control *por_reset;
77 struct reset_control *phy_reset;
78 + struct reset_control *ext_reset;
79 struct regulator *vdda;
80 struct regulator *vdda_phy;
81 struct regulator *vdda_refclk;
82 + uint8_t phy_tx0_term_offset;
85 struct qcom_pcie_resources_v1 {
86 @@ -106,20 +152,10 @@ writel_masked(void __iomem *addr, u32 cl
88 static void qcom_ep_reset_assert_deassert(struct qcom_pcie *pcie, int assert)
90 - int val, active_low;
92 if (IS_ERR_OR_NULL(pcie->reset))
95 - active_low = gpiod_is_active_low(pcie->reset);
102 - gpiod_set_value(pcie->reset, val);
104 + gpiod_set_value(pcie->reset, assert);
105 usleep_range(PERST_DELAY_MIN_US, PERST_DELAY_MAX_US);
108 @@ -156,10 +192,13 @@ static void qcom_pcie_disable_resources_
109 reset_control_assert(res->axi_reset);
110 reset_control_assert(res->ahb_reset);
111 reset_control_assert(res->por_reset);
112 - reset_control_assert(res->pci_reset);
113 + reset_control_assert(res->phy_reset);
114 + reset_control_assert(res->ext_reset);
115 clk_disable_unprepare(res->iface_clk);
116 clk_disable_unprepare(res->core_clk);
117 clk_disable_unprepare(res->phy_clk);
118 + clk_disable_unprepare(res->aux_clk);
119 + clk_disable_unprepare(res->ref_clk);
120 regulator_disable(res->vdda);
121 regulator_disable(res->vdda_phy);
122 regulator_disable(res->vdda_refclk);
123 @@ -201,6 +240,12 @@ static int qcom_pcie_enable_resources_v0
127 + ret = reset_control_deassert(res->ext_reset);
129 + dev_err(dev, "cannot assert ext reset\n");
130 + goto err_reset_ext;
133 ret = clk_prepare_enable(res->iface_clk);
135 dev_err(dev, "cannot prepare/enable iface clock\n");
136 @@ -219,21 +264,40 @@ static int qcom_pcie_enable_resources_v0
140 + ret = clk_prepare_enable(res->aux_clk);
142 + dev_err(dev, "cannot prepare/enable aux clock\n");
146 + ret = clk_prepare_enable(res->ref_clk);
148 + dev_err(dev, "cannot prepare/enable ref clock\n");
152 ret = reset_control_deassert(res->ahb_reset);
154 dev_err(dev, "cannot deassert ahb reset\n");
162 + clk_disable_unprepare(res->ref_clk);
164 + clk_disable_unprepare(res->aux_clk);
166 clk_disable_unprepare(res->phy_clk);
168 clk_disable_unprepare(res->core_clk);
170 clk_disable_unprepare(res->iface_clk);
172 + reset_control_assert(res->ext_reset);
174 regulator_disable(res->vdda_phy);
176 regulator_disable(res->vdda_refclk);
177 @@ -329,6 +393,14 @@ static int qcom_pcie_get_resources_v0(st
178 if (IS_ERR(res->phy_clk))
179 return PTR_ERR(res->phy_clk);
181 + res->aux_clk = devm_clk_get(dev, "aux");
182 + if (IS_ERR(res->aux_clk))
183 + return PTR_ERR(res->aux_clk);
185 + res->ref_clk = devm_clk_get(dev, "ref");
186 + if (IS_ERR(res->ref_clk))
187 + return PTR_ERR(res->ref_clk);
189 res->pci_reset = devm_reset_control_get(dev, "pci");
190 if (IS_ERR(res->pci_reset))
191 return PTR_ERR(res->pci_reset);
192 @@ -349,6 +421,14 @@ static int qcom_pcie_get_resources_v0(st
193 if (IS_ERR(res->phy_reset))
194 return PTR_ERR(res->phy_reset);
196 + res->ext_reset = devm_reset_control_get(dev, "ext");
197 + if (IS_ERR(res->ext_reset))
198 + return PTR_ERR(res->ext_reset);
200 + if (of_property_read_u8(dev->of_node, "phy-tx0-term-offset",
201 + &res->phy_tx0_term_offset))
202 + res->phy_tx0_term_offset = 0;
207 @@ -461,6 +541,57 @@ err_res:
208 qcom_pcie_disable_resources_v1(pcie);
211 +static void qcom_pcie_prog_viewport_cfg0(struct qcom_pcie *pcie, u32 busdev)
213 + struct pcie_port *pp = &pcie->pp;
216 + * program and enable address translation region 0 (device config
217 + * address space); region type config;
218 + * axi config address range to device config address range
220 + writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
221 + PCIE20_PLR_IATU_REGION_INDEX(0),
222 + pcie->dbi + PCIE20_PLR_IATU_VIEWPORT);
224 + writel(PCIE20_PLR_IATU_TYPE_CFG0, pcie->dbi + PCIE20_PLR_IATU_CTRL1);
225 + writel(PCIE20_PLR_IATU_ENABLE, pcie->dbi + PCIE20_PLR_IATU_CTRL2);
226 + writel(pp->cfg0_mod_base, pcie->dbi + PCIE20_PLR_IATU_LBAR);
227 + writel((pp->cfg0_mod_base >> 32), pcie->dbi + PCIE20_PLR_IATU_UBAR);
228 + writel((pp->cfg0_mod_base + pp->cfg0_size - 1),
229 + pcie->dbi + PCIE20_PLR_IATU_LAR);
230 + writel(busdev, pcie->dbi + PCIE20_PLR_IATU_LTAR);
231 + writel(0, pcie->dbi + PCIE20_PLR_IATU_UTAR);
234 +static void qcom_pcie_prog_viewport_mem2_outbound(struct qcom_pcie *pcie)
236 + struct pcie_port *pp = &pcie->pp;
239 + * program and enable address translation region 2 (device resource
240 + * address space); region type memory;
241 + * axi device bar address range to device bar address range
243 + writel(PCIE20_PLR_IATU_REGION_OUTBOUND |
244 + PCIE20_PLR_IATU_REGION_INDEX(2),
245 + pcie->dbi + PCIE20_PLR_IATU_VIEWPORT);
247 + writel(PCIE20_PLR_IATU_TYPE_MEM, pcie->dbi + PCIE20_PLR_IATU_CTRL1);
248 + writel(PCIE20_PLR_IATU_ENABLE, pcie->dbi + PCIE20_PLR_IATU_CTRL2);
249 + writel(pp->mem_mod_base, pcie->dbi + PCIE20_PLR_IATU_LBAR);
250 + writel((pp->mem_mod_base >> 32), pcie->dbi + PCIE20_PLR_IATU_UBAR);
251 + writel(pp->mem_mod_base + pp->mem_size - 1,
252 + pcie->dbi + PCIE20_PLR_IATU_LAR);
253 + writel(pp->mem_bus_addr, pcie->dbi + PCIE20_PLR_IATU_LTAR);
254 + writel(upper_32_bits(pp->mem_bus_addr),
255 + pcie->dbi + PCIE20_PLR_IATU_UTAR);
257 + /* 256B PCIE buffer setting */
258 + writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL0);
259 + writel(0x1, pcie->dbi + PCIE20_AXI_MSTR_RESP_COMP_CTRL1);
262 static void qcom_pcie_host_init_v0(struct pcie_port *pp)
264 struct qcom_pcie *pcie = to_qcom_pcie(pp);
265 @@ -470,15 +601,34 @@ static void qcom_pcie_host_init_v0(struc
267 qcom_ep_reset_assert(pcie);
269 + reset_control_assert(res->ahb_reset);
271 ret = qcom_pcie_enable_resources_v0(pcie);
275 writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
277 - /* enable external reference clock */
278 - writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK, 0, BIT(16));
279 + /* Set Tx termination offset */
280 + writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL,
281 + PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK,
282 + PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset));
284 + /* PARF programming */
285 + writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) |
286 + PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) |
287 + PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22),
288 + pcie->parf + PCIE20_PARF_PCS_DEEMPH);
289 + writel(PCS_SWING_TX_SWING_FULL(0x78) |
290 + PCS_SWING_TX_SWING_LOW(0x78),
291 + pcie->parf + PCIE20_PARF_PCS_SWING);
292 + writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
294 + /* Enable reference clock */
295 + writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK,
296 + REF_USE_PAD, REF_SSP_EN);
298 + /* De-assert PHY, PCIe, POR and AXI resets */
299 ret = reset_control_deassert(res->phy_reset);
301 dev_err(dev, "cannot deassert phy reset\n");
302 @@ -517,6 +667,9 @@ static void qcom_pcie_host_init_v0(struc
306 + qcom_pcie_prog_viewport_cfg0(pcie, MSM_PCIE_DEV_CFG_ADDR);
307 + qcom_pcie_prog_viewport_mem2_outbound(pcie);
311 qcom_ep_reset_assert(pcie);