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4 Subject: [v3,02/13] clk: mux: Split out register accessors for reuse
5 From: Stephen Boyd <sboyd@codeaurora.org>
6 X-Patchwork-Id: 6063111
7 Message-Id: <1426920332-9340-3-git-send-email-sboyd@codeaurora.org>
8 To: Mike Turquette <mturquette@linaro.org>, Stephen Boyd <sboyd@codeaurora.org>
9 Cc: linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
10 linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
11 Viresh Kumar <viresh.kumar@linaro.org>
12 Date: Fri, 20 Mar 2015 23:45:21 -0700
14 We want to reuse the logic in clk-mux.c for other clock drivers
15 that don't use readl as register accessors. Fortunately, there
16 really isn't much to the mux code besides the table indirection
17 and quirk flags if you assume any bit shifting and masking has
18 been done already. Pull that logic out into reusable functions
19 that operate on an optional table and some flags so that other
20 drivers can use the same logic.
22 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
25 drivers/clk/clk-mux.c | 76 +++++++++++++++++++++++++++-----------------
26 include/linux/clk-provider.h | 9 ++++--
27 2 files changed, 54 insertions(+), 31 deletions(-)
29 --- a/drivers/clk/clk-mux.c
30 +++ b/drivers/clk/clk-mux.c
33 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
35 -static u8 clk_mux_get_parent(struct clk_hw *hw)
36 +unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
37 + unsigned int *table, unsigned long flags)
39 - struct clk_mux *mux = to_clk_mux(hw);
40 int num_parents = __clk_get_num_parents(hw->clk);
44 - * FIXME need a mux-specific flag to determine if val is bitwise or numeric
45 - * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
46 - * to 0x7 (index starts at one)
47 - * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
48 - * val = 0x4 really means "bit 2, index starts at bit 0"
50 - val = clk_readl(mux->reg) >> mux->shift;
57 for (i = 0; i < num_parents; i++)
58 - if (mux->table[i] == val)
59 + if (table[i] == val)
64 - if (val && (mux->flags & CLK_MUX_INDEX_BIT))
65 + if (val && (flags & CLK_MUX_INDEX_BIT))
68 - if (val && (mux->flags & CLK_MUX_INDEX_ONE))
69 + if (val && (flags & CLK_MUX_INDEX_ONE))
72 if (val >= num_parents)
73 @@ -65,24 +54,53 @@ static u8 clk_mux_get_parent(struct clk_
77 +EXPORT_SYMBOL_GPL(clk_mux_get_parent);
79 -static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
80 +static u8 _clk_mux_get_parent(struct clk_hw *hw)
82 struct clk_mux *mux = to_clk_mux(hw);
84 - unsigned long flags = 0;
87 - index = mux->table[index];
89 + * FIXME need a mux-specific flag to determine if val is bitwise or numeric
90 + * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
91 + * to 0x7 (index starts at one)
92 + * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
93 + * val = 0x4 really means "bit 2, index starts at bit 0"
95 + val = clk_readl(mux->reg) >> mux->shift;
98 + return clk_mux_get_parent(hw, val, mux->table, mux->flags);
102 - if (mux->flags & CLK_MUX_INDEX_BIT)
103 - index = 1 << index;
104 +unsigned int clk_mux_reindex(u8 index, unsigned int *table,
105 + unsigned long flags)
107 + unsigned int val = index;
109 - if (mux->flags & CLK_MUX_INDEX_ONE)
114 + if (flags & CLK_MUX_INDEX_BIT)
117 + if (flags & CLK_MUX_INDEX_ONE)
123 +EXPORT_SYMBOL_GPL(clk_mux_reindex);
125 +static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
127 + struct clk_mux *mux = to_clk_mux(hw);
129 + unsigned long flags = 0;
131 + index = clk_mux_reindex(index, mux->table, mux->flags);
134 spin_lock_irqsave(mux->lock, flags);
136 @@ -102,21 +120,21 @@ static int clk_mux_set_parent(struct clk
139 const struct clk_ops clk_mux_ops = {
140 - .get_parent = clk_mux_get_parent,
141 + .get_parent = _clk_mux_get_parent,
142 .set_parent = clk_mux_set_parent,
143 .determine_rate = __clk_mux_determine_rate,
145 EXPORT_SYMBOL_GPL(clk_mux_ops);
147 const struct clk_ops clk_mux_ro_ops = {
148 - .get_parent = clk_mux_get_parent,
149 + .get_parent = _clk_mux_get_parent,
151 EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
153 struct clk *clk_register_mux_table(struct device *dev, const char *name,
154 const char **parent_names, u8 num_parents, unsigned long flags,
155 void __iomem *reg, u8 shift, u32 mask,
156 - u8 clk_mux_flags, u32 *table, spinlock_t *lock)
157 + u8 clk_mux_flags, unsigned int *table, spinlock_t *lock)
161 --- a/include/linux/clk-provider.h
162 +++ b/include/linux/clk-provider.h
163 @@ -390,7 +390,7 @@ void clk_unregister_divider(struct clk *
168 + unsigned int *table;
172 @@ -406,6 +406,11 @@ struct clk_mux {
173 extern const struct clk_ops clk_mux_ops;
174 extern const struct clk_ops clk_mux_ro_ops;
176 +unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
177 + unsigned int *table, unsigned long flags);
178 +unsigned int clk_mux_reindex(u8 index, unsigned int *table,
179 + unsigned long flags);
181 struct clk *clk_register_mux(struct device *dev, const char *name,
182 const char **parent_names, u8 num_parents, unsigned long flags,
183 void __iomem *reg, u8 shift, u8 width,
184 @@ -414,7 +419,7 @@ struct clk *clk_register_mux(struct devi
185 struct clk *clk_register_mux_table(struct device *dev, const char *name,
186 const char **parent_names, u8 num_parents, unsigned long flags,
187 void __iomem *reg, u8 shift, u32 mask,
188 - u8 clk_mux_flags, u32 *table, spinlock_t *lock);
189 + u8 clk_mux_flags, unsigned int *table, spinlock_t *lock);
191 void clk_unregister_mux(struct clk *clk);