1 From cab1f4720e82f2e17eaeed9a9ad9e4f07c742977 Mon Sep 17 00:00:00 2001
2 From: Mathieu Olivari <mathieu@codeaurora.org>
3 Date: Mon, 11 May 2015 12:29:18 -0700
4 Subject: [PATCH 8/8] ARM: dts: qcom: add gmac nodes to ipq806x platforms
6 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
8 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 31 ++++++++++++
9 arch/arm/boot/dts/qcom-ipq8064-db149.dts | 43 ++++++++++++++++
10 arch/arm/boot/dts/qcom-ipq8064.dtsi | 86 ++++++++++++++++++++++++++++++++
11 3 files changed, 160 insertions(+)
13 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
14 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
20 + rgmii2_pins: rgmii2_pins {
22 + pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
23 + "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
24 + function = "rgmii2";
25 + drive-strength = <8>;
37 + gmac1: ethernet@37200000 {
42 + pinctrl-0 = <&rgmii2_pins>;
43 + pinctrl-names = "default";
51 + gmac2: ethernet@37400000 {
64 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
65 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
71 + rgmii0_pins: rgmii0_pins {
73 + pins = "gpio2", "gpio66";
74 + drive-strength = <8>;
80 gsbi2: gsbi@12480000 {
86 + gmac0: ethernet@37000000 {
90 + phy-handle = <&phy4>;
92 + pinctrl-0 = <&rgmii0_pins>;
93 + pinctrl-names = "default";
96 + gmac1: ethernet@37200000 {
107 + gmac2: ethernet@37400000 {
109 + phy-mode = "sgmii";
111 + phy-handle = <&phy6>;
114 + gmac3: ethernet@37600000 {
116 + phy-mode = "sgmii";
118 + phy-handle = <&phy7>;
122 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
123 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
128 + nss_common: syscon@03000000 {
129 + compatible = "syscon";
130 + reg = <0x03000000 0x0000FFFF>;
133 + qsgmii_csr: syscon@1bb00000 {
134 + compatible = "syscon";
135 + reg = <0x1bb00000 0x000001FF>;
138 + gmac0: ethernet@37000000 {
139 + device_type = "network";
140 + compatible = "qcom,ipq806x-gmac";
141 + reg = <0x37000000 0x200000>;
142 + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
143 + interrupt-names = "macirq";
145 + qcom,nss-common = <&nss_common>;
146 + qcom,qsgmii-csr = <&qsgmii_csr>;
148 + clocks = <&gcc GMAC_CORE1_CLK>;
149 + clock-names = "stmmaceth";
151 + resets = <&gcc GMAC_CORE1_RESET>;
152 + reset-names = "stmmaceth";
154 + status = "disabled";
157 + gmac1: ethernet@37200000 {
158 + device_type = "network";
159 + compatible = "qcom,ipq806x-gmac";
160 + reg = <0x37200000 0x200000>;
161 + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
162 + interrupt-names = "macirq";
164 + qcom,nss-common = <&nss_common>;
165 + qcom,qsgmii-csr = <&qsgmii_csr>;
167 + clocks = <&gcc GMAC_CORE2_CLK>;
168 + clock-names = "stmmaceth";
170 + resets = <&gcc GMAC_CORE2_RESET>;
171 + reset-names = "stmmaceth";
173 + status = "disabled";
176 + gmac2: ethernet@37400000 {
177 + device_type = "network";
178 + compatible = "qcom,ipq806x-gmac";
179 + reg = <0x37400000 0x200000>;
180 + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
181 + interrupt-names = "macirq";
183 + qcom,nss-common = <&nss_common>;
184 + qcom,qsgmii-csr = <&qsgmii_csr>;
186 + clocks = <&gcc GMAC_CORE3_CLK>;
187 + clock-names = "stmmaceth";
189 + resets = <&gcc GMAC_CORE3_RESET>;
190 + reset-names = "stmmaceth";
192 + status = "disabled";
195 + gmac3: ethernet@37600000 {
196 + device_type = "network";
197 + compatible = "qcom,ipq806x-gmac";
198 + reg = <0x37600000 0x200000>;
199 + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
200 + interrupt-names = "macirq";
202 + qcom,nss-common = <&nss_common>;
203 + qcom,qsgmii-csr = <&qsgmii_csr>;
205 + clocks = <&gcc GMAC_CORE4_CLK>;
206 + clock-names = "stmmaceth";
208 + resets = <&gcc GMAC_CORE4_RESET>;
209 + reset-names = "stmmaceth";
211 + status = "disabled";
216 sfpb_mutex: sfpb-mutex {