1 Content-Type: text/plain; charset="utf-8"
3 Content-Transfer-Encoding: 7bit
4 Subject: [v2,3/5] DT: PCI: qcom: Document PCIe devicetree bindings
5 From: Stanimir Varbanov <svarbanov@mm-sol.com>
6 X-Patchwork-Id: 6326181
7 Message-Id: <1430743338-10441-4-git-send-email-svarbanov@mm-sol.com>
8 To: Rob Herring <robh+dt@kernel.org>, Kumar Gala <galak@codeaurora.org>,
9 Mark Rutland <mark.rutland@arm.com>,
10 Grant Likely <grant.likely@linaro.org>,
11 Bjorn Helgaas <bhelgaas@google.com>,
12 Kishon Vijay Abraham I <kishon@ti.com>,
13 Russell King <linux@arm.linux.org.uk>, Arnd Bergmann <arnd@arndb.de>
14 Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
15 linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
16 linux-pci@vger.kernel.org, Mathieu Olivari <mathieu@codeaurora.org>,
17 Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
18 Stanimir Varbanov <svarbanov@mm-sol.com>
19 Date: Mon, 4 May 2015 15:42:16 +0300
21 Document Qualcomm PCIe driver devicetree bindings.
23 Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
26 .../devicetree/bindings/pci/qcom,pcie.txt | 231 ++++++++++++++++++++
27 1 files changed, 231 insertions(+), 0 deletions(-)
28 create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie.txt
31 +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
33 +* Qualcomm PCI express root complex
37 + Value type: <stringlist>
38 + Definition: Value shall include
39 + - "qcom,pcie-v0" for apq/ipq8064
40 + - "qcom,pcie-v1" for apq8084
44 + Value type: <prop-encoded-array>
45 + Definition: Register ranges as listed in the reg-names property
49 + Value type: <stringlist>
50 + Definition: Must include the following entries
51 + - "parf" Qualcomm specific registers
52 + - "dbi" Designware PCIe registers
53 + - "elbi" External local bus interface registers
54 + - "config" PCIe configuration space
58 + Value type: <string>
59 + Definition: Should be "pci". As specified in designware-pcie.txt
64 + Definition: Should be set to 3. As specified in designware-pcie.txt
69 + Definition: Should be set 2. As specified in designware-pcie.txt
73 + Value type: <prop-encoded-array>
74 + Definition: As specified in designware-pcie.txt
78 + Value type: <prop-encoded-array>
79 + Definition: MSI interrupt
83 + Value type: <stringlist>
84 + Definition: Should contain "msi"
89 + Definition: Should be 1. As specified in designware-pcie.txt
91 +- interrupt-map-mask:
93 + Value type: <prop-encoded-array>
94 + Definition: As specified in designware-pcie.txt
98 + Value type: <prop-encoded-array>
99 + Definition: As specified in designware-pcie.txt
103 + Value type: <prop-encoded-array>
104 + Definition: List of phandle and clock specifier pairs as listed
105 + in clock-names property
109 + Value type: <stringlist>
110 + Definition: Should contain the following entries
111 + * should be populated for v0 and v1
112 + - "iface" Configuration AHB clock
114 + * should be populated for v0
115 + - "core" Clocks the pcie hw block
116 + - "phy" Clocks the pcie PHY block
118 + * should be populated for v1
119 + - "aux" Auxiliary (AUX) clock
120 + - "bus_master" Master AXI clock
121 + - "bus_slave" Slave AXI clock
125 + Value type: <prop-encoded-array>
126 + Definition: List of phandle and reset specifier pairs as listed
127 + in reset-names property
131 + Value type: <stringlist>
132 + Definition: Should contain the following entries
133 + * should be populated for v0
140 + * should be populated for v1
141 + - "core" Core reset
144 + Usage: required (for v1 only)
145 + Value type: <prop-encoded-array>
146 + Definition: A phandle and power domain specifier pair to the
147 + power domain which is responsible for collapsing
148 + and restoring power to the peripheral
152 + Value type: <phandle>
153 + Definition: List of phandles to the power supply regulator(s)
154 + * should be populated for v0 and v1
155 + - "vdda" core analog power supply
157 + * should be populated for v0
158 + - "vdda_phy" analog power supply for PHY
159 + - "vdda_refclk" analog power supply for IC which generate
163 + Usage: required (for v1 only)
164 + Value type: <phandle>
165 + Definition: List of phandle(s) as listed in phy-names property
168 + Usage: required (for v1 only)
169 + Value type: <stringlist>
170 + Definition: Should contain "pciephy"
174 + Value type: <prop-encoded-array>
175 + Definition: List of phandle and gpio specifier pairs. Should contain
176 + - "perst" PCIe endpoint reset signal line
177 + - "pewake" PCIe endpoint wake signal line
181 + Value type: <phandle>
182 + Definition: List of phandles pointing at a pin(s) configuration
186 + Value type: <stringlist>
187 + Definition: List of names of pinctrl-0 state
190 + pcie0: pci@1b500000 {
191 + compatible = "qcom,pcie-v0";
192 + reg = <0x1b500000 0x1000
195 + 0x0ff00000 0x100000>;
196 + reg-names = "dbi", "elbi", "parf", "config";
197 + device_type = "pci";
198 + linux,pci-domain = <0>;
199 + bus-range = <0x00 0xff>;
201 + #address-cells = <3>;
203 + ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
204 + 0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* memory */
205 + interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
206 + interrupt-names = "msi";
207 + #interrupt-cells = <1>;
208 + interrupt-map-mask = <0 0 0 0x7>;
209 + interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
210 + <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
211 + <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
212 + <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
213 + clocks = <&gcc PCIE_A_CLK>,
215 + <&gcc PCIE_PHY_CLK>;
216 + clock-names = "core", "iface", "phy";
217 + resets = <&gcc PCIE_ACLK_RESET>,
218 + <&gcc PCIE_HCLK_RESET>,
219 + <&gcc PCIE_POR_RESET>,
220 + <&gcc PCIE_PCI_RESET>,
221 + <&gcc PCIE_PHY_RESET>;
222 + reset-names = "axi", "ahb", "por", "pci", "phy";
227 + compatible = "qcom,pcie-v1";
228 + reg = <0xfc520000 0x2000>,
229 + <0xff000000 0x1000>,
230 + <0xff001000 0x1000>,
231 + <0xff002000 0x2000>;
232 + reg-names = "parf", "dbi", "elbi", "config";
233 + device_type = "pci";
234 + linux,pci-domain = <0>;
235 + bus-range = <0x00 0xff>;
237 + #address-cells = <3>;
239 + ranges = <0x81000000 0 0 0xff200000 0 0x00100000 /* I/O */
240 + 0x82000000 0 0x00300000 0xff300000 0 0x00d00000>; /* memory */
241 + interrupts = <GIC_SPI 243 IRQ_TYPE_NONE>;
242 + interrupt-names = "msi";
243 + #interrupt-cells = <1>;
244 + interrupt-map-mask = <0 0 0 0x7>;
245 + interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
246 + <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
247 + <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
248 + <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
249 + clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
250 + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
251 + <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
252 + <&gcc GCC_PCIE_0_AUX_CLK>;
253 + clock-names = "iface", "master_bus", "slave_bus", "aux";
254 + resets = <&gcc GCC_PCIE_0_BCR>;
255 + reset-names = "core";
256 + power-domains = <&gcc PCIE0_GDSC>;
257 + vdda-supply = <&pma8084_l3>;
258 + phys = <&pciephy0>;
259 + phy-names = "pciephy";
260 + perst-gpio = <&tlmm 70 GPIO_ACTIVE_LOW>;
261 + pinctrl-0 = <&pcie0_pins_default>;
262 + pinctrl-names = "default";