1 Content-Type: text/plain; charset="utf-8"
3 Content-Transfer-Encoding: 7bit
4 Subject: [v2,4/5] PCI: qcom: Add Qualcomm PCIe controller driver
5 From: Stanimir Varbanov <svarbanov@mm-sol.com>
6 X-Patchwork-Id: 6326161
7 Message-Id: <1430743338-10441-5-git-send-email-svarbanov@mm-sol.com>
8 To: Rob Herring <robh+dt@kernel.org>, Kumar Gala <galak@codeaurora.org>,
9 Mark Rutland <mark.rutland@arm.com>,
10 Grant Likely <grant.likely@linaro.org>,
11 Bjorn Helgaas <bhelgaas@google.com>,
12 Kishon Vijay Abraham I <kishon@ti.com>,
13 Russell King <linux@arm.linux.org.uk>, Arnd Bergmann <arnd@arndb.de>
14 Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
15 linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
16 linux-pci@vger.kernel.org, Mathieu Olivari <mathieu@codeaurora.org>,
17 Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
18 Stanimir Varbanov <svarbanov@mm-sol.com>
19 Date: Mon, 4 May 2015 15:42:17 +0300
21 The PCIe driver reuse the Designware common code for host
22 and MSI initialization, and also program the Qualcomm
23 application specific registers.
25 Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
29 drivers/pci/host/Kconfig | 9 +
30 drivers/pci/host/Makefile | 1 +
31 drivers/pci/host/pcie-qcom.c | 677 ++++++++++++++++++++++++++++++++++++++++++
32 4 files changed, 694 insertions(+), 0 deletions(-)
33 create mode 100644 drivers/pci/host/pcie-qcom.c
37 @@ -7511,6 +7511,13 @@ L: linux-pci@vger.kernel.org
39 F: drivers/pci/host/*spear*
41 +PCIE DRIVER FOR QUALCOMM MSM
42 +M: Stanimir Varbanov <svarbanov@mm-sol.com>
43 +L: linux-pci@vger.kernel.org
44 +L: linux-arm-msm@vger.kernel.org
46 +F: drivers/pci/host/*qcom*
50 L: linux-pcmcia@lists.infradead.org
51 --- a/drivers/pci/host/Kconfig
52 +++ b/drivers/pci/host/Kconfig
53 @@ -106,4 +106,13 @@ config PCI_VERSATILE
54 bool "ARM Versatile PB PCI controller"
55 depends on ARCH_VERSATILE
58 + bool "Qualcomm PCIe controller"
59 + depends on ARCH_QCOM && OF || (ARM && COMPILE_TEST)
63 + Say Y here to enable PCIe controller support on Qualcomm SoCs. The
64 + PCIe controller use Designware core plus Qualcomm specific hardware
68 +++ b/drivers/pci/host/pcie-qcom.c
71 + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
73 + * This program is free software; you can redistribute it and/or modify
74 + * it under the terms of the GNU General Public License version 2 and
75 + * only version 2 as published by the Free Software Foundation.
77 + * This program is distributed in the hope that it will be useful,
78 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
79 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
80 + * GNU General Public License for more details.
83 +#include <linux/clk.h>
84 +#include <linux/delay.h>
85 +#include <linux/gpio.h>
86 +#include <linux/interrupt.h>
87 +#include <linux/io.h>
88 +#include <linux/kernel.h>
89 +#include <linux/module.h>
90 +#include <linux/of_gpio.h>
91 +#include <linux/pci.h>
92 +#include <linux/platform_device.h>
93 +#include <linux/phy/phy.h>
94 +#include <linux/regulator/consumer.h>
95 +#include <linux/reset.h>
96 +#include <linux/slab.h>
97 +#include <linux/types.h>
99 +#include "pcie-designware.h"
101 +#define PCIE20_PARF_PHY_CTRL 0x40
102 +#define PCIE20_PARF_PHY_REFCLK 0x4C
103 +#define PCIE20_PARF_DBI_BASE_ADDR 0x168
104 +#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16c
105 +#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x178
107 +#define PCIE20_ELBI_SYS_CTRL 0x04
108 +#define PCIE20_ELBI_SYS_STTS 0x08
109 +#define XMLH_LINK_UP BIT(10)
111 +#define PCIE20_CAP 0x70
112 +#define PCIE20_CAP_LINKCTRLSTATUS (PCIE20_CAP + 0x10)
114 +#define PERST_DELAY_MIN_US 1000
115 +#define PERST_DELAY_MAX_US 1005
117 +#define LINKUP_DELAY_MIN_US 5000
118 +#define LINKUP_DELAY_MAX_US 5100
119 +#define LINKUP_RETRIES_COUNT 20
121 +#define PCIE_V0 0 /* apq8064 */
122 +#define PCIE_V1 1 /* apq8084 */
124 +struct qcom_pcie_resources_v0 {
125 + struct clk *iface_clk;
126 + struct clk *core_clk;
127 + struct clk *phy_clk;
128 + struct reset_control *pci_reset;
129 + struct reset_control *axi_reset;
130 + struct reset_control *ahb_reset;
131 + struct reset_control *por_reset;
132 + struct reset_control *phy_reset;
133 + struct regulator *vdda;
134 + struct regulator *vdda_phy;
135 + struct regulator *vdda_refclk;
138 +struct qcom_pcie_resources_v1 {
141 + struct clk *master_bus;
142 + struct clk *slave_bus;
143 + struct reset_control *core;
144 + struct regulator *vdda;
147 +union pcie_resources {
148 + struct qcom_pcie_resources_v0 v0;
149 + struct qcom_pcie_resources_v1 v1;
153 + struct pcie_port pp;
154 + struct device *dev;
155 + union pcie_resources res;
156 + void __iomem *parf;
158 + void __iomem *elbi;
160 + struct gpio_desc *reset;
161 + unsigned int version;
164 +#define to_qcom_pcie(x) container_of(x, struct qcom_pcie, pp)
167 +writel_masked(void __iomem *addr, u32 clear_mask, u32 set_mask)
169 + u32 val = readl(addr);
171 + val &= ~clear_mask;
176 +static void qcom_ep_reset_assert_deassert(struct qcom_pcie *pcie, int assert)
178 + int val, active_low;
180 + if (IS_ERR_OR_NULL(pcie->reset))
183 + active_low = gpiod_is_active_low(pcie->reset);
186 + val = !!active_low;
190 + gpiod_set_value(pcie->reset, val);
192 + usleep_range(PERST_DELAY_MIN_US, PERST_DELAY_MAX_US);
195 +static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
197 + qcom_ep_reset_assert_deassert(pcie, 1);
200 +static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
202 + qcom_ep_reset_assert_deassert(pcie, 0);
205 +static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg)
207 + struct pcie_port *pp = arg;
209 + return dw_handle_msi_irq(pp);
212 +static int qcom_pcie_link_up(struct pcie_port *pp)
214 + struct qcom_pcie *pcie = to_qcom_pcie(pp);
215 + u32 val = readl(pcie->dbi + PCIE20_CAP_LINKCTRLSTATUS);
217 + return val & BIT(29) ? 1 : 0;
220 +static void qcom_pcie_disable_resources_v0(struct qcom_pcie *pcie)
222 + struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
224 + reset_control_assert(res->pci_reset);
225 + reset_control_assert(res->axi_reset);
226 + reset_control_assert(res->ahb_reset);
227 + reset_control_assert(res->por_reset);
228 + reset_control_assert(res->pci_reset);
229 + clk_disable_unprepare(res->iface_clk);
230 + clk_disable_unprepare(res->core_clk);
231 + clk_disable_unprepare(res->phy_clk);
232 + regulator_disable(res->vdda);
233 + regulator_disable(res->vdda_phy);
234 + regulator_disable(res->vdda_refclk);
237 +static void qcom_pcie_disable_resources_v1(struct qcom_pcie *pcie)
239 + struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
241 + reset_control_assert(res->core);
242 + clk_disable_unprepare(res->slave_bus);
243 + clk_disable_unprepare(res->master_bus);
244 + clk_disable_unprepare(res->iface);
245 + clk_disable_unprepare(res->aux);
246 + regulator_disable(res->vdda);
249 +static int qcom_pcie_enable_resources_v0(struct qcom_pcie *pcie)
251 + struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
252 + struct device *dev = pcie->dev;
255 + ret = regulator_enable(res->vdda);
257 + dev_err(dev, "cannot enable vdda regulator\n");
261 + ret = regulator_enable(res->vdda_refclk);
263 + dev_err(dev, "cannot enable vdda_refclk regulator\n");
267 + ret = regulator_enable(res->vdda_phy);
269 + dev_err(dev, "cannot enable vdda_phy regulator\n");
273 + ret = clk_prepare_enable(res->iface_clk);
275 + dev_err(dev, "cannot prepare/enable iface clock\n");
279 + ret = clk_prepare_enable(res->core_clk);
281 + dev_err(dev, "cannot prepare/enable core clock\n");
285 + ret = clk_prepare_enable(res->phy_clk);
287 + dev_err(dev, "cannot prepare/enable phy clock\n");
291 + ret = reset_control_deassert(res->ahb_reset);
293 + dev_err(dev, "cannot deassert ahb reset\n");
294 + goto err_reset_ahb;
300 + clk_disable_unprepare(res->phy_clk);
302 + clk_disable_unprepare(res->core_clk);
304 + clk_disable_unprepare(res->iface_clk);
306 + regulator_disable(res->vdda_phy);
308 + regulator_disable(res->vdda_refclk);
310 + regulator_disable(res->vdda);
314 +static int qcom_pcie_enable_resources_v1(struct qcom_pcie *pcie)
316 + struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
317 + struct device *dev = pcie->dev;
320 + ret = reset_control_deassert(res->core);
322 + dev_err(dev, "cannot deassert core reset\n");
326 + ret = clk_prepare_enable(res->aux);
328 + dev_err(dev, "cannot prepare/enable aux clock\n");
332 + ret = clk_prepare_enable(res->iface);
334 + dev_err(dev, "cannot prepare/enable iface clock\n");
338 + ret = clk_prepare_enable(res->master_bus);
340 + dev_err(dev, "cannot prepare/enable master_bus clock\n");
344 + ret = clk_prepare_enable(res->slave_bus);
346 + dev_err(dev, "cannot prepare/enable slave_bus clock\n");
350 + ret = regulator_enable(res->vdda);
352 + dev_err(dev, "cannot enable vdda regulator\n");
359 + clk_disable_unprepare(res->slave_bus);
361 + clk_disable_unprepare(res->master_bus);
363 + clk_disable_unprepare(res->iface);
365 + clk_disable_unprepare(res->aux);
367 + reset_control_assert(res->core);
372 +static int qcom_pcie_get_resources_v0(struct qcom_pcie *pcie)
374 + struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
375 + struct device *dev = pcie->dev;
377 + res->vdda = devm_regulator_get(dev, "vdda");
378 + if (IS_ERR(res->vdda))
379 + return PTR_ERR(res->vdda);
381 + res->vdda_phy = devm_regulator_get(dev, "vdda_phy");
382 + if (IS_ERR(res->vdda_phy))
383 + return PTR_ERR(res->vdda_phy);
385 + res->vdda_refclk = devm_regulator_get(dev, "vdda_refclk");
386 + if (IS_ERR(res->vdda_refclk))
387 + return PTR_ERR(res->vdda_refclk);
389 + res->iface_clk = devm_clk_get(dev, "iface");
390 + if (IS_ERR(res->iface_clk))
391 + return PTR_ERR(res->iface_clk);
393 + res->core_clk = devm_clk_get(dev, "core");
394 + if (IS_ERR(res->core_clk))
395 + return PTR_ERR(res->core_clk);
397 + res->phy_clk = devm_clk_get(dev, "phy");
398 + if (IS_ERR(res->phy_clk))
399 + return PTR_ERR(res->phy_clk);
401 + res->pci_reset = devm_reset_control_get(dev, "pci");
402 + if (IS_ERR(res->pci_reset))
403 + return PTR_ERR(res->pci_reset);
405 + res->axi_reset = devm_reset_control_get(dev, "axi");
406 + if (IS_ERR(res->axi_reset))
407 + return PTR_ERR(res->axi_reset);
409 + res->ahb_reset = devm_reset_control_get(dev, "ahb");
410 + if (IS_ERR(res->ahb_reset))
411 + return PTR_ERR(res->ahb_reset);
413 + res->por_reset = devm_reset_control_get(dev, "por");
414 + if (IS_ERR(res->por_reset))
415 + return PTR_ERR(res->por_reset);
417 + res->phy_reset = devm_reset_control_get(dev, "phy");
418 + if (IS_ERR(res->phy_reset))
419 + return PTR_ERR(res->phy_reset);
424 +static int qcom_pcie_get_resources_v1(struct qcom_pcie *pcie)
426 + struct qcom_pcie_resources_v1 *res = &pcie->res.v1;
427 + struct device *dev = pcie->dev;
429 + res->vdda = devm_regulator_get(dev, "vdda");
430 + if (IS_ERR(res->vdda))
431 + return PTR_ERR(res->vdda);
433 + res->iface = devm_clk_get(dev, "iface");
434 + if (IS_ERR(res->iface))
435 + return PTR_ERR(res->iface);
437 + res->aux = devm_clk_get(dev, "aux");
438 + if (IS_ERR(res->aux) && PTR_ERR(res->aux) == -EPROBE_DEFER)
439 + return -EPROBE_DEFER;
440 + else if (IS_ERR(res->aux))
443 + res->master_bus = devm_clk_get(dev, "master_bus");
444 + if (IS_ERR(res->master_bus))
445 + return PTR_ERR(res->master_bus);
447 + res->slave_bus = devm_clk_get(dev, "slave_bus");
448 + if (IS_ERR(res->slave_bus))
449 + return PTR_ERR(res->slave_bus);
451 + res->core = devm_reset_control_get(dev, "core");
452 + if (IS_ERR(res->core))
453 + return PTR_ERR(res->core);
458 +static int qcom_pcie_enable_link_training(struct pcie_port *pp)
460 + struct qcom_pcie *pcie = to_qcom_pcie(pp);
461 + struct device *dev = pp->dev;
465 + /* enable link training */
466 + writel_masked(pcie->elbi + PCIE20_ELBI_SYS_CTRL, 0, BIT(0));
468 + /* wait for up to 100ms for the link to come up */
469 + retries = LINKUP_RETRIES_COUNT;
471 + val = readl(pcie->elbi + PCIE20_ELBI_SYS_STTS);
472 + if (val & XMLH_LINK_UP)
474 + usleep_range(LINKUP_DELAY_MIN_US, LINKUP_DELAY_MAX_US);
475 + } while (retries--);
477 + if (retries < 0 || !dw_pcie_link_up(pp)) {
478 + dev_err(dev, "link initialization failed\n");
485 +static void qcom_pcie_host_init_v1(struct pcie_port *pp)
487 + struct qcom_pcie *pcie = to_qcom_pcie(pp);
490 + qcom_ep_reset_assert(pcie);
492 + ret = qcom_pcie_enable_resources_v1(pcie);
496 + /* change DBI base address */
497 + writel(0, pcie->parf + PCIE20_PARF_DBI_BASE_ADDR);
499 + if (IS_ENABLED(CONFIG_PCI_MSI))
500 + writel_masked(pcie->parf + PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT,
503 + ret = phy_init(pcie->phy);
507 + ret = phy_power_on(pcie->phy);
511 + dw_pcie_setup_rc(pp);
513 + if (IS_ENABLED(CONFIG_PCI_MSI))
514 + dw_pcie_msi_init(pp);
516 + qcom_ep_reset_deassert(pcie);
518 + ret = qcom_pcie_enable_link_training(pp);
525 + qcom_ep_reset_assert(pcie);
526 + phy_power_off(pcie->phy);
528 + phy_exit(pcie->phy);
530 + qcom_pcie_disable_resources_v1(pcie);
533 +static void qcom_pcie_host_init_v0(struct pcie_port *pp)
535 + struct qcom_pcie *pcie = to_qcom_pcie(pp);
536 + struct qcom_pcie_resources_v0 *res = &pcie->res.v0;
537 + struct device *dev = pcie->dev;
540 + qcom_ep_reset_assert(pcie);
542 + ret = qcom_pcie_enable_resources_v0(pcie);
546 + writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
548 + /* enable external reference clock */
549 + writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK, 0, BIT(16));
551 + ret = reset_control_deassert(res->phy_reset);
553 + dev_err(dev, "cannot deassert phy reset\n");
557 + ret = reset_control_deassert(res->pci_reset);
559 + dev_err(dev, "cannot deassert pci reset\n");
563 + ret = reset_control_deassert(res->por_reset);
565 + dev_err(dev, "cannot deassert por reset\n");
569 + ret = reset_control_deassert(res->axi_reset);
571 + dev_err(dev, "cannot deassert axi reset\n");
575 + /* wait 150ms for clock acquisition */
576 + usleep_range(10000, 15000);
578 + dw_pcie_setup_rc(pp);
580 + if (IS_ENABLED(CONFIG_PCI_MSI))
581 + dw_pcie_msi_init(pp);
583 + qcom_ep_reset_deassert(pcie);
585 + ret = qcom_pcie_enable_link_training(pp);
591 + qcom_ep_reset_assert(pcie);
592 + qcom_pcie_disable_resources_v0(pcie);
595 +static void qcom_pcie_host_init(struct pcie_port *pp)
597 + struct qcom_pcie *pcie = to_qcom_pcie(pp);
599 + if (pcie->version == PCIE_V0)
600 + return qcom_pcie_host_init_v0(pp);
602 + return qcom_pcie_host_init_v1(pp);
606 +qcom_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val)
608 + /* the device class is not reported correctly from the register */
609 + if (where == PCI_CLASS_REVISION && size == 4) {
610 + *val = readl(pp->dbi_base + PCI_CLASS_REVISION);
611 + *val &= ~(0xffff << 16);
612 + *val |= PCI_CLASS_BRIDGE_PCI << 16;
613 + return PCIBIOS_SUCCESSFUL;
616 + return dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
620 +static struct pcie_host_ops qcom_pcie_ops = {
621 + .link_up = qcom_pcie_link_up,
622 + .host_init = qcom_pcie_host_init,
623 + .rd_own_conf = qcom_pcie_rd_own_conf,
626 +static const struct of_device_id qcom_pcie_match[] = {
627 + { .compatible = "qcom,pcie-v0", .data = (void *)PCIE_V0 },
628 + { .compatible = "qcom,pcie-v1", .data = (void *)PCIE_V1 },
632 +static int qcom_pcie_probe(struct platform_device *pdev)
634 + struct device *dev = &pdev->dev;
635 + const struct of_device_id *match;
636 + struct resource *res;
637 + struct qcom_pcie *pcie;
638 + struct pcie_port *pp;
641 + match = of_match_node(qcom_pcie_match, dev->of_node);
645 + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
649 + pcie->version = (unsigned int)match->data;
651 + pcie->reset = devm_gpiod_get_optional(dev, "perst");
652 + if (IS_ERR(pcie->reset) && PTR_ERR(pcie->reset) == -EPROBE_DEFER)
653 + return PTR_ERR(pcie->reset);
655 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
656 + pcie->parf = devm_ioremap_resource(dev, res);
657 + if (IS_ERR(pcie->parf))
658 + return PTR_ERR(pcie->parf);
660 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
661 + pcie->dbi = devm_ioremap_resource(dev, res);
662 + if (IS_ERR(pcie->dbi))
663 + return PTR_ERR(pcie->dbi);
665 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
666 + pcie->elbi = devm_ioremap_resource(dev, res);
667 + if (IS_ERR(pcie->elbi))
668 + return PTR_ERR(pcie->elbi);
670 + pcie->phy = devm_phy_optional_get(dev, "pciephy");
671 + if (IS_ERR(pcie->phy))
672 + return PTR_ERR(pcie->phy);
676 + if (pcie->version == PCIE_V0)
677 + ret = qcom_pcie_get_resources_v0(pcie);
679 + ret = qcom_pcie_get_resources_v1(pcie);
686 + pp->dbi_base = pcie->dbi;
687 + pp->root_bus_nr = -1;
688 + pp->ops = &qcom_pcie_ops;
690 + if (IS_ENABLED(CONFIG_PCI_MSI)) {
691 + pp->msi_irq = platform_get_irq_byname(pdev, "msi");
692 + if (pp->msi_irq < 0) {
693 + dev_err(dev, "cannot get msi irq\n");
694 + return pp->msi_irq;
697 + ret = devm_request_irq(dev, pp->msi_irq,
698 + qcom_pcie_msi_irq_handler,
699 + IRQF_SHARED, "qcom-pcie-msi", pp);
701 + dev_err(dev, "cannot request msi irq\n");
706 + ret = dw_pcie_host_init(pp);
708 + dev_err(dev, "cannot initialize host\n");
712 + platform_set_drvdata(pdev, pcie);
717 +static int qcom_pcie_remove(struct platform_device *pdev)
719 + struct qcom_pcie *pcie = platform_get_drvdata(pdev);
721 + qcom_ep_reset_assert(pcie);
722 + phy_power_off(pcie->phy);
723 + phy_exit(pcie->phy);
724 + if (pcie->version == PCIE_V0)
725 + qcom_pcie_disable_resources_v0(pcie);
727 + qcom_pcie_disable_resources_v1(pcie);
732 +static struct platform_driver qcom_pcie_driver = {
733 + .probe = qcom_pcie_probe,
734 + .remove = qcom_pcie_remove,
736 + .name = "qcom-pcie",
737 + .of_match_table = qcom_pcie_match,
741 +module_platform_driver(qcom_pcie_driver);
743 +MODULE_AUTHOR("Stanimir Varbanov <svarbanov@mm-sol.com>");
744 +MODULE_DESCRIPTION("Qualcomm PCIe root complex driver");
745 +MODULE_LICENSE("GPL v2");
746 +MODULE_ALIAS("platform:qcom-pcie");
747 --- a/drivers/pci/host/Makefile
748 +++ b/drivers/pci/host/Makefile
749 @@ -13,3 +13,4 @@ obj-$(CONFIG_PCIE_XILINX) += pcie-xilinx
750 obj-$(CONFIG_PCI_XGENE) += pci-xgene.o
751 obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
752 obj-$(CONFIG_PCI_VERSATILE) += pci-versatile.o
753 +obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o