1 From 5b40516b2f5fb9b2a7d6d3e2e924f12ec9d183a8 Mon Sep 17 00:00:00 2001
2 From: Mathieu Olivari <mathieu@codeaurora.org>
3 Date: Tue, 21 Apr 2015 19:01:42 -0700
4 Subject: [PATCH 8/9] ARM: dts: qcom: add pcie nodes to ipq806x platforms
6 qcom-pcie driver now supports version 0 of the controller. This change
7 adds the corresponding entries to the IPQ806x dtsi file and
8 corresponding platform (AP148).
10 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
12 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 30 ++++++++
13 arch/arm/boot/dts/qcom-ipq8064.dtsi | 124 +++++++++++++++++++++++++++++++
14 2 files changed, 154 insertions(+)
16 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
17 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
22 + pcie1_pins: pcie1_pinmux {
25 + drive-strength = <2>;
30 + pcie2_pins: pcie2_pinmux {
33 + drive-strength = <2>;
40 pins = "gpio18", "gpio19", "gpio21";
46 + pcie0: pci@1b500000 {
48 + reset-gpio = <&qcom_pinmux 3 0>;
49 + pinctrl-0 = <&pcie1_pins>;
50 + pinctrl-names = "default";
53 + pcie1: pci@1b700000 {
55 + reset-gpio = <&qcom_pinmux 48 0>;
56 + pinctrl-0 = <&pcie2_pins>;
57 + pinctrl-names = "default";
61 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
62 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
67 + pcie1_pins: pcie1_pinmux {
70 + drive-strength = <2>;
75 + pcie2_pins: pcie2_pinmux {
78 + drive-strength = <2>;
83 + pcie3_pins: pcie3_pinmux {
86 + drive-strength = <2>;
93 pins = "gpio18", "gpio19", "gpio21";
99 + pcie0: pci@1b500000 {
101 + reset-gpio = <&qcom_pinmux 3 0>;
102 + pinctrl-0 = <&pcie1_pins>;
103 + pinctrl-names = "default";
106 + pcie1: pci@1b700000 {
108 + reset-gpio = <&qcom_pinmux 48 0>;
109 + pinctrl-0 = <&pcie2_pins>;
110 + pinctrl-names = "default";
113 + pcie2: pci@1b900000 {
115 + reset-gpio = <&qcom_pinmux 63 0>;
116 + pinctrl-0 = <&pcie3_pins>;
117 + pinctrl-names = "default";
121 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
122 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
124 #include "skeleton.dtsi"
125 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
126 #include <dt-bindings/soc/qcom,gsbi.h>
127 +#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
128 +#include <include/dt-bindings/interrupt-controller/arm-gic.h>
131 model = "Qualcomm IPQ8064";
132 @@ -291,5 +293,128 @@
137 + pcie0: pci@1b500000 {
138 + compatible = "qcom,pcie-v0";
139 + reg = <0x1b500000 0x1000
142 + 0x0ff00000 0x100000>;
143 + reg-names = "dbi", "elbi", "parf", "config";
144 + device_type = "pci";
145 + linux,pci-domain = <0>;
146 + bus-range = <0x00 0xff>;
148 + #address-cells = <3>;
151 + ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* downstream I/O */
152 + 0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
154 + interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
155 + interrupt-names = "msi";
156 + #interrupt-cells = <1>;
157 + interrupt-map-mask = <0 0 0 0x7>;
158 + interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
159 + <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
160 + <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
161 + <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
163 + clocks = <&gcc PCIE_A_CLK>,
165 + <&gcc PCIE_PHY_CLK>;
166 + clock-names = "core", "iface", "phy";
168 + resets = <&gcc PCIE_ACLK_RESET>,
169 + <&gcc PCIE_HCLK_RESET>,
170 + <&gcc PCIE_POR_RESET>,
171 + <&gcc PCIE_PCI_RESET>,
172 + <&gcc PCIE_PHY_RESET>;
173 + reset-names = "axi", "ahb", "por", "pci", "phy";
175 + status = "disabled";
178 + pcie1: pci@1b700000 {
179 + compatible = "qcom,pcie-v0";
180 + reg = <0x1b700000 0x1000
183 + 0x31f00000 0x100000>;
184 + reg-names = "dbi", "elbi", "parf", "config";
185 + device_type = "pci";
186 + linux,pci-domain = <1>;
187 + bus-range = <0x00 0xff>;
189 + #address-cells = <3>;
192 + ranges = <0x81000000 0 0 0x31e00000 0 0x00100000 /* downstream I/O */
193 + 0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
195 + interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
196 + interrupt-names = "msi";
197 + #interrupt-cells = <1>;
198 + interrupt-map-mask = <0 0 0 0x7>;
199 + interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
200 + <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
201 + <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
202 + <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
204 + clocks = <&gcc PCIE_1_A_CLK>,
205 + <&gcc PCIE_1_H_CLK>,
206 + <&gcc PCIE_1_PHY_CLK>;
207 + clock-names = "core", "iface", "phy";
209 + resets = <&gcc PCIE_1_ACLK_RESET>,
210 + <&gcc PCIE_1_HCLK_RESET>,
211 + <&gcc PCIE_1_POR_RESET>,
212 + <&gcc PCIE_1_PCI_RESET>,
213 + <&gcc PCIE_1_PHY_RESET>;
214 + reset-names = "axi", "ahb", "por", "pci", "phy";
216 + status = "disabled";
219 + pcie2: pci@1b900000 {
220 + compatible = "qcom,pcie-v0";
221 + reg = <0x1b900000 0x1000
224 + 0x35f00000 0x100000>;
225 + reg-names = "dbi", "elbi", "parf", "config";
226 + device_type = "pci";
227 + linux,pci-domain = <2>;
228 + bus-range = <0x00 0xff>;
230 + #address-cells = <3>;
233 + ranges = <0x81000000 0 0 0x35e00000 0 0x00100000 /* downstream I/O */
234 + 0x82000000 0 0x00000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
236 + interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
237 + interrupt-names = "msi";
238 + #interrupt-cells = <1>;
239 + interrupt-map-mask = <0 0 0 0x7>;
240 + interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
241 + <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
242 + <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
243 + <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
245 + clocks = <&gcc PCIE_2_A_CLK>,
246 + <&gcc PCIE_2_H_CLK>,
247 + <&gcc PCIE_2_PHY_CLK>;
248 + clock-names = "core", "iface", "phy";
250 + resets = <&gcc PCIE_2_ACLK_RESET>,
251 + <&gcc PCIE_2_HCLK_RESET>,
252 + <&gcc PCIE_2_POR_RESET>,
253 + <&gcc PCIE_2_PCI_RESET>,
254 + <&gcc PCIE_2_PHY_RESET>;
255 + reset-names = "axi", "ahb", "por", "pci", "phy";
257 + status = "disabled";