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ipq806x: move arm-gic include into pcie patch
[openwrt/staging/wigyori.git] / target / linux / ipq806x / patches-4.0 / 112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
1 From 5b40516b2f5fb9b2a7d6d3e2e924f12ec9d183a8 Mon Sep 17 00:00:00 2001
2 From: Mathieu Olivari <mathieu@codeaurora.org>
3 Date: Tue, 21 Apr 2015 19:01:42 -0700
4 Subject: [PATCH 8/9] ARM: dts: qcom: add pcie nodes to ipq806x platforms
5
6 qcom-pcie driver now supports version 0 of the controller. This change
7 adds the corresponding entries to the IPQ806x dtsi file and
8 corresponding platform (AP148).
9
10 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
11 ---
12 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 30 ++++++++
13 arch/arm/boot/dts/qcom-ipq8064.dtsi | 124 +++++++++++++++++++++++++++++++
14 2 files changed, 154 insertions(+)
15
16 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
17 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
18 @@ -30,6 +30,22 @@
19 bias-disable;
20 };
21
22 + pcie1_pins: pcie1_pinmux {
23 + mux {
24 + pins = "gpio3";
25 + drive-strength = <2>;
26 + bias-disable;
27 + };
28 + };
29 +
30 + pcie2_pins: pcie2_pinmux {
31 + mux {
32 + pins = "gpio48";
33 + drive-strength = <2>;
34 + bias-disable;
35 + };
36 + };
37 +
38 spi_pins: spi_pins {
39 mux {
40 pins = "gpio18", "gpio19", "gpio21";
41 @@ -109,5 +125,19 @@
42 sata@29000000 {
43 status = "ok";
44 };
45 +
46 + pcie0: pci@1b500000 {
47 + status = "ok";
48 + reset-gpio = <&qcom_pinmux 3 0>;
49 + pinctrl-0 = <&pcie1_pins>;
50 + pinctrl-names = "default";
51 + };
52 +
53 + pcie1: pci@1b700000 {
54 + status = "ok";
55 + reset-gpio = <&qcom_pinmux 48 0>;
56 + pinctrl-0 = <&pcie2_pins>;
57 + pinctrl-names = "default";
58 + };
59 };
60 };
61 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
62 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
63 @@ -37,6 +37,30 @@
64 bias-disable;
65 };
66
67 + pcie1_pins: pcie1_pinmux {
68 + mux {
69 + pins = "gpio3";
70 + drive-strength = <2>;
71 + bias-disable;
72 + };
73 + };
74 +
75 + pcie2_pins: pcie2_pinmux {
76 + mux {
77 + pins = "gpio48";
78 + drive-strength = <2>;
79 + bias-disable;
80 + };
81 + };
82 +
83 + pcie3_pins: pcie3_pinmux {
84 + mux {
85 + pins = "gpio63";
86 + drive-strength = <2>;
87 + bias-disable;
88 + };
89 + };
90 +
91 spi_pins: spi_pins {
92 mux {
93 pins = "gpio18", "gpio19", "gpio21";
94 @@ -153,6 +177,27 @@
95 status = "ok";
96 };
97
98 + pcie0: pci@1b500000 {
99 + status = "ok";
100 + reset-gpio = <&qcom_pinmux 3 0>;
101 + pinctrl-0 = <&pcie1_pins>;
102 + pinctrl-names = "default";
103 + };
104 +
105 + pcie1: pci@1b700000 {
106 + status = "ok";
107 + reset-gpio = <&qcom_pinmux 48 0>;
108 + pinctrl-0 = <&pcie2_pins>;
109 + pinctrl-names = "default";
110 + };
111 +
112 + pcie2: pci@1b900000 {
113 + status = "ok";
114 + reset-gpio = <&qcom_pinmux 63 0>;
115 + pinctrl-0 = <&pcie3_pins>;
116 + pinctrl-names = "default";
117 + };
118 +
119 mdio0: mdio {
120 compatible = "virtual,mdio-gpio";
121 #address-cells = <1>;
122 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
123 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
124 @@ -3,6 +3,8 @@
125 #include "skeleton.dtsi"
126 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
127 #include <dt-bindings/soc/qcom,gsbi.h>
128 +#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
129 +#include <include/dt-bindings/interrupt-controller/arm-gic.h>
130
131 / {
132 model = "Qualcomm IPQ8064";
133 @@ -291,5 +292,128 @@
134 #clock-cells = <1>;
135 #reset-cells = <1>;
136 };
137 +
138 + pcie0: pci@1b500000 {
139 + compatible = "qcom,pcie-v0";
140 + reg = <0x1b500000 0x1000
141 + 0x1b502000 0x80
142 + 0x1b600000 0x100
143 + 0x0ff00000 0x100000>;
144 + reg-names = "dbi", "elbi", "parf", "config";
145 + device_type = "pci";
146 + linux,pci-domain = <0>;
147 + bus-range = <0x00 0xff>;
148 + num-lanes = <1>;
149 + #address-cells = <3>;
150 + #size-cells = <2>;
151 +
152 + ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* downstream I/O */
153 + 0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
154 +
155 + interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
156 + interrupt-names = "msi";
157 + #interrupt-cells = <1>;
158 + interrupt-map-mask = <0 0 0 0x7>;
159 + interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
160 + <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
161 + <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
162 + <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
163 +
164 + clocks = <&gcc PCIE_A_CLK>,
165 + <&gcc PCIE_H_CLK>,
166 + <&gcc PCIE_PHY_CLK>;
167 + clock-names = "core", "iface", "phy";
168 +
169 + resets = <&gcc PCIE_ACLK_RESET>,
170 + <&gcc PCIE_HCLK_RESET>,
171 + <&gcc PCIE_POR_RESET>,
172 + <&gcc PCIE_PCI_RESET>,
173 + <&gcc PCIE_PHY_RESET>;
174 + reset-names = "axi", "ahb", "por", "pci", "phy";
175 +
176 + status = "disabled";
177 + };
178 +
179 + pcie1: pci@1b700000 {
180 + compatible = "qcom,pcie-v0";
181 + reg = <0x1b700000 0x1000
182 + 0x1b702000 0x80
183 + 0x1b800000 0x100
184 + 0x31f00000 0x100000>;
185 + reg-names = "dbi", "elbi", "parf", "config";
186 + device_type = "pci";
187 + linux,pci-domain = <1>;
188 + bus-range = <0x00 0xff>;
189 + num-lanes = <1>;
190 + #address-cells = <3>;
191 + #size-cells = <2>;
192 +
193 + ranges = <0x81000000 0 0 0x31e00000 0 0x00100000 /* downstream I/O */
194 + 0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
195 +
196 + interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
197 + interrupt-names = "msi";
198 + #interrupt-cells = <1>;
199 + interrupt-map-mask = <0 0 0 0x7>;
200 + interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
201 + <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
202 + <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
203 + <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
204 +
205 + clocks = <&gcc PCIE_1_A_CLK>,
206 + <&gcc PCIE_1_H_CLK>,
207 + <&gcc PCIE_1_PHY_CLK>;
208 + clock-names = "core", "iface", "phy";
209 +
210 + resets = <&gcc PCIE_1_ACLK_RESET>,
211 + <&gcc PCIE_1_HCLK_RESET>,
212 + <&gcc PCIE_1_POR_RESET>,
213 + <&gcc PCIE_1_PCI_RESET>,
214 + <&gcc PCIE_1_PHY_RESET>;
215 + reset-names = "axi", "ahb", "por", "pci", "phy";
216 +
217 + status = "disabled";
218 + };
219 +
220 + pcie2: pci@1b900000 {
221 + compatible = "qcom,pcie-v0";
222 + reg = <0x1b900000 0x1000
223 + 0x1b902000 0x80
224 + 0x1ba00000 0x100
225 + 0x35f00000 0x100000>;
226 + reg-names = "dbi", "elbi", "parf", "config";
227 + device_type = "pci";
228 + linux,pci-domain = <2>;
229 + bus-range = <0x00 0xff>;
230 + num-lanes = <1>;
231 + #address-cells = <3>;
232 + #size-cells = <2>;
233 +
234 + ranges = <0x81000000 0 0 0x35e00000 0 0x00100000 /* downstream I/O */
235 + 0x82000000 0 0x00000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
236 +
237 + interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
238 + interrupt-names = "msi";
239 + #interrupt-cells = <1>;
240 + interrupt-map-mask = <0 0 0 0x7>;
241 + interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
242 + <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
243 + <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
244 + <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
245 +
246 + clocks = <&gcc PCIE_2_A_CLK>,
247 + <&gcc PCIE_2_H_CLK>,
248 + <&gcc PCIE_2_PHY_CLK>;
249 + clock-names = "core", "iface", "phy";
250 +
251 + resets = <&gcc PCIE_2_ACLK_RESET>,
252 + <&gcc PCIE_2_HCLK_RESET>,
253 + <&gcc PCIE_2_POR_RESET>,
254 + <&gcc PCIE_2_PCI_RESET>,
255 + <&gcc PCIE_2_PHY_RESET>;
256 + reset-names = "axi", "ahb", "por", "pci", "phy";
257 +
258 + status = "disabled";
259 + };
260 };
261 };
Staging tree of Zoltan Herpai