1 From 2fbb18f85826a9ba308fedb2cf90d3a661a39fd7 Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Fri, 27 Mar 2015 00:16:14 -0700
4 Subject: [PATCH] clk: qcom: Add support for NSS/GMAC clocks and resets
6 Add the NSS/GMAC clocks and the TCM clock and NSS resets.
8 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
10 drivers/clk/qcom/gcc-ipq806x.c | 594 ++++++++++++++++++++++++++-
11 drivers/clk/qcom/gcc-ipq806x.c.rej | 50 +++
12 include/dt-bindings/clock/qcom,gcc-ipq806x.h | 2 +
13 include/dt-bindings/reset/qcom,gcc-ipq806x.h | 43 ++
14 4 files changed, 688 insertions(+), 1 deletion(-)
15 create mode 100644 drivers/clk/qcom/gcc-ipq806x.c.rej
17 --- a/drivers/clk/qcom/gcc-ipq806x.c
18 +++ b/drivers/clk/qcom/gcc-ipq806x.c
19 @@ -220,11 +220,46 @@ static struct clk_regmap pll14_vote = {
23 +#define NSS_PLL_RATE(f, _l, _m, _n, i) \
32 +static struct pll_freq_tbl pll18_freq_tbl[] = {
33 + NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
34 + NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
37 +static struct clk_pll pll18 = {
41 + .config_reg = 0x31b4,
43 + .status_reg = 0x31b8,
45 + .post_div_shift = 16,
46 + .post_div_width = 1,
47 + .freq_tbl = pll18_freq_tbl,
48 + .clkr.hw.init = &(struct clk_init_data){
50 + .parent_names = (const char *[]){ "pxo" },
52 + .ops = &clk_pll_ops,
64 static const u8 gcc_pxo_pll8_map[] = {
66 @@ -275,6 +310,22 @@ static const char *gcc_pxo_pll8_pll0_map
70 +static const u8 gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
78 +static const char *gcc_pxo_pll8_pll14_pll18_pll0[] = {
86 static struct freq_tbl clk_tbl_gsbi_uart[] = {
87 { 1843200, P_PLL8, 2, 6, 625 },
88 { 3686400, P_PLL8, 2, 12, 625 },
89 @@ -2250,6 +2301,472 @@ static struct clk_branch usb_fs1_h_clk =
93 +static const struct freq_tbl clk_tbl_gmac[] = {
94 + { 133000000, P_PLL0, 1, 50, 301 },
95 + { 266000000, P_PLL0, 1, 127, 382 },
99 +static struct clk_dyn_rcg gmac_core1_src = {
100 + .ns_reg[0] = 0x3cac,
101 + .ns_reg[1] = 0x3cb0,
102 + .md_reg[0] = 0x3ca4,
103 + .md_reg[1] = 0x3ca8,
104 + .bank_reg = 0x3ca0,
107 + .mnctr_reset_bit = 7,
108 + .mnctr_mode_shift = 5,
115 + .mnctr_reset_bit = 7,
116 + .mnctr_mode_shift = 5,
122 + .src_sel_shift = 0,
123 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
126 + .src_sel_shift = 0,
127 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
130 + .pre_div_shift = 3,
131 + .pre_div_width = 2,
134 + .pre_div_shift = 3,
135 + .pre_div_width = 2,
138 + .freq_tbl = clk_tbl_gmac,
140 + .enable_reg = 0x3ca0,
141 + .enable_mask = BIT(1),
142 + .hw.init = &(struct clk_init_data){
143 + .name = "gmac_core1_src",
144 + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
146 + .ops = &clk_dyn_rcg_ops,
151 +static struct clk_branch gmac_core1_clk = {
152 + .halt_reg = 0x3c20,
154 + .hwcg_reg = 0x3cb4,
157 + .enable_reg = 0x3cb4,
158 + .enable_mask = BIT(4),
159 + .hw.init = &(struct clk_init_data){
160 + .name = "gmac_core1_clk",
161 + .parent_names = (const char *[]){
165 + .ops = &clk_branch_ops,
166 + .flags = CLK_SET_RATE_PARENT,
171 +static struct clk_dyn_rcg gmac_core2_src = {
172 + .ns_reg[0] = 0x3ccc,
173 + .ns_reg[1] = 0x3cd0,
174 + .md_reg[0] = 0x3cc4,
175 + .md_reg[1] = 0x3cc8,
176 + .bank_reg = 0x3ca0,
179 + .mnctr_reset_bit = 7,
180 + .mnctr_mode_shift = 5,
187 + .mnctr_reset_bit = 7,
188 + .mnctr_mode_shift = 5,
194 + .src_sel_shift = 0,
195 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
198 + .src_sel_shift = 0,
199 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
202 + .pre_div_shift = 3,
203 + .pre_div_width = 2,
206 + .pre_div_shift = 3,
207 + .pre_div_width = 2,
210 + .freq_tbl = clk_tbl_gmac,
212 + .enable_reg = 0x3cc0,
213 + .enable_mask = BIT(1),
214 + .hw.init = &(struct clk_init_data){
215 + .name = "gmac_core2_src",
216 + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
218 + .ops = &clk_dyn_rcg_ops,
223 +static struct clk_branch gmac_core2_clk = {
224 + .halt_reg = 0x3c20,
226 + .hwcg_reg = 0x3cd4,
229 + .enable_reg = 0x3cd4,
230 + .enable_mask = BIT(4),
231 + .hw.init = &(struct clk_init_data){
232 + .name = "gmac_core2_clk",
233 + .parent_names = (const char *[]){
237 + .ops = &clk_branch_ops,
238 + .flags = CLK_SET_RATE_PARENT,
243 +static struct clk_dyn_rcg gmac_core3_src = {
244 + .ns_reg[0] = 0x3cec,
245 + .ns_reg[1] = 0x3cf0,
246 + .md_reg[0] = 0x3ce4,
247 + .md_reg[1] = 0x3ce8,
248 + .bank_reg = 0x3ce0,
251 + .mnctr_reset_bit = 7,
252 + .mnctr_mode_shift = 5,
259 + .mnctr_reset_bit = 7,
260 + .mnctr_mode_shift = 5,
266 + .src_sel_shift = 0,
267 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
270 + .src_sel_shift = 0,
271 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
274 + .pre_div_shift = 3,
275 + .pre_div_width = 2,
278 + .pre_div_shift = 3,
279 + .pre_div_width = 2,
282 + .freq_tbl = clk_tbl_gmac,
284 + .enable_reg = 0x3ce0,
285 + .enable_mask = BIT(1),
286 + .hw.init = &(struct clk_init_data){
287 + .name = "gmac_core3_src",
288 + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
290 + .ops = &clk_dyn_rcg_ops,
295 +static struct clk_branch gmac_core3_clk = {
296 + .halt_reg = 0x3c20,
298 + .hwcg_reg = 0x3cf4,
301 + .enable_reg = 0x3cf4,
302 + .enable_mask = BIT(4),
303 + .hw.init = &(struct clk_init_data){
304 + .name = "gmac_core3_clk",
305 + .parent_names = (const char *[]){
309 + .ops = &clk_branch_ops,
310 + .flags = CLK_SET_RATE_PARENT,
315 +static struct clk_dyn_rcg gmac_core4_src = {
316 + .ns_reg[0] = 0x3d0c,
317 + .ns_reg[1] = 0x3d10,
318 + .md_reg[0] = 0x3d04,
319 + .md_reg[1] = 0x3d08,
320 + .bank_reg = 0x3d00,
323 + .mnctr_reset_bit = 7,
324 + .mnctr_mode_shift = 5,
331 + .mnctr_reset_bit = 7,
332 + .mnctr_mode_shift = 5,
338 + .src_sel_shift = 0,
339 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
342 + .src_sel_shift = 0,
343 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
346 + .pre_div_shift = 3,
347 + .pre_div_width = 2,
350 + .pre_div_shift = 3,
351 + .pre_div_width = 2,
354 + .freq_tbl = clk_tbl_gmac,
356 + .enable_reg = 0x3d00,
357 + .enable_mask = BIT(1),
358 + .hw.init = &(struct clk_init_data){
359 + .name = "gmac_core4_src",
360 + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
362 + .ops = &clk_dyn_rcg_ops,
367 +static struct clk_branch gmac_core4_clk = {
368 + .halt_reg = 0x3c20,
370 + .hwcg_reg = 0x3d14,
373 + .enable_reg = 0x3d14,
374 + .enable_mask = BIT(4),
375 + .hw.init = &(struct clk_init_data){
376 + .name = "gmac_core4_clk",
377 + .parent_names = (const char *[]){
381 + .ops = &clk_branch_ops,
382 + .flags = CLK_SET_RATE_PARENT,
387 +static const struct freq_tbl clk_tbl_nss_tcm[] = {
388 + { 266000000, P_PLL0, 3, 0, 0 },
389 + { 400000000, P_PLL0, 2, 0, 0 },
393 +static struct clk_dyn_rcg nss_tcm_src = {
394 + .ns_reg[0] = 0x3dc4,
395 + .ns_reg[1] = 0x3dc8,
396 + .bank_reg = 0x3dc0,
398 + .src_sel_shift = 0,
399 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
402 + .src_sel_shift = 0,
403 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
406 + .pre_div_shift = 3,
407 + .pre_div_width = 4,
410 + .pre_div_shift = 3,
411 + .pre_div_width = 4,
414 + .freq_tbl = clk_tbl_nss_tcm,
416 + .enable_reg = 0x3dc0,
417 + .enable_mask = BIT(1),
418 + .hw.init = &(struct clk_init_data){
419 + .name = "nss_tcm_src",
420 + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
422 + .ops = &clk_dyn_rcg_ops,
427 +static struct clk_branch nss_tcm_clk = {
428 + .halt_reg = 0x3c20,
431 + .enable_reg = 0x3dd0,
432 + .enable_mask = BIT(6) | BIT(4),
433 + .hw.init = &(struct clk_init_data){
434 + .name = "nss_tcm_clk",
435 + .parent_names = (const char *[]){
439 + .ops = &clk_branch_ops,
440 + .flags = CLK_SET_RATE_PARENT,
445 +static const struct freq_tbl clk_tbl_nss[] = {
446 + { 110000000, P_PLL18, 1, 1, 5 },
447 + { 275000000, P_PLL18, 2, 0, 0 },
448 + { 550000000, P_PLL18, 1, 0, 0 },
449 + { 733000000, P_PLL18, 1, 0, 0 },
453 +static struct clk_dyn_rcg ubi32_core1_src_clk = {
454 + .ns_reg[0] = 0x3d2c,
455 + .ns_reg[1] = 0x3d30,
456 + .md_reg[0] = 0x3d24,
457 + .md_reg[1] = 0x3d28,
458 + .bank_reg = 0x3d20,
461 + .mnctr_reset_bit = 7,
462 + .mnctr_mode_shift = 5,
469 + .mnctr_reset_bit = 7,
470 + .mnctr_mode_shift = 5,
476 + .src_sel_shift = 0,
477 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
480 + .src_sel_shift = 0,
481 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
484 + .pre_div_shift = 3,
485 + .pre_div_width = 2,
488 + .pre_div_shift = 3,
489 + .pre_div_width = 2,
492 + .freq_tbl = clk_tbl_nss,
494 + .enable_reg = 0x3d20,
495 + .enable_mask = BIT(1),
496 + .hw.init = &(struct clk_init_data){
497 + .name = "ubi32_core1_src_clk",
498 + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
500 + .ops = &clk_dyn_rcg_ops,
501 + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
506 +static struct clk_dyn_rcg ubi32_core2_src_clk = {
507 + .ns_reg[0] = 0x3d4c,
508 + .ns_reg[1] = 0x3d50,
509 + .md_reg[0] = 0x3d44,
510 + .md_reg[1] = 0x3d48,
511 + .bank_reg = 0x3d40,
514 + .mnctr_reset_bit = 7,
515 + .mnctr_mode_shift = 5,
522 + .mnctr_reset_bit = 7,
523 + .mnctr_mode_shift = 5,
529 + .src_sel_shift = 0,
530 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
533 + .src_sel_shift = 0,
534 + .parent_map = gcc_pxo_pll8_pll14_pll18_pll0_map,
537 + .pre_div_shift = 3,
538 + .pre_div_width = 2,
541 + .pre_div_shift = 3,
542 + .pre_div_width = 2,
545 + .freq_tbl = clk_tbl_nss,
547 + .enable_reg = 0x3d40,
548 + .enable_mask = BIT(1),
549 + .hw.init = &(struct clk_init_data){
550 + .name = "ubi32_core2_src_clk",
551 + .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
553 + .ops = &clk_dyn_rcg_ops,
554 + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
559 static struct clk_regmap *gcc_ipq806x_clks[] = {
561 [PLL0_VOTE] = &pll0_vote,
562 @@ -2259,6 +2776,7 @@ static struct clk_regmap *gcc_ipq806x_cl
563 [PLL8_VOTE] = &pll8_vote,
564 [PLL14] = &pll14.clkr,
565 [PLL14_VOTE] = &pll14_vote,
566 + [PLL18] = &pll18.clkr,
567 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
568 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
569 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
570 @@ -2356,6 +2874,18 @@ static struct clk_regmap *gcc_ipq806x_cl
571 [PLL9] = &hfpll0.clkr,
572 [PLL10] = &hfpll1.clkr,
573 [PLL12] = &hfpll_l2.clkr,
574 + [GMAC_CORE1_CLK_SRC] = &gmac_core1_src.clkr,
575 + [GMAC_CORE1_CLK] = &gmac_core1_clk.clkr,
576 + [GMAC_CORE2_CLK_SRC] = &gmac_core2_src.clkr,
577 + [GMAC_CORE2_CLK] = &gmac_core2_clk.clkr,
578 + [GMAC_CORE3_CLK_SRC] = &gmac_core3_src.clkr,
579 + [GMAC_CORE3_CLK] = &gmac_core3_clk.clkr,
580 + [GMAC_CORE4_CLK_SRC] = &gmac_core4_src.clkr,
581 + [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr,
582 + [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr,
583 + [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
584 + [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
585 + [NSSTCM_CLK] = &nss_tcm_clk.clkr,
588 static const struct qcom_reset_map gcc_ipq806x_resets[] = {
589 @@ -2474,6 +3004,48 @@ static const struct qcom_reset_map gcc_i
590 [USB30_1_PHY_RESET] = { 0x3b58, 0 },
591 [NSSFB0_RESET] = { 0x3b60, 6 },
592 [NSSFB1_RESET] = { 0x3b60, 7 },
593 + [UBI32_CORE1_CLKRST_CLAMP_RESET] = { 0x3d3c, 3},
594 + [UBI32_CORE1_CLAMP_RESET] = { 0x3d3c, 2 },
595 + [UBI32_CORE1_AHB_RESET] = { 0x3d3c, 1 },
596 + [UBI32_CORE1_AXI_RESET] = { 0x3d3c, 0 },
597 + [UBI32_CORE2_CLKRST_CLAMP_RESET] = { 0x3d5c, 3 },
598 + [UBI32_CORE2_CLAMP_RESET] = { 0x3d5c, 2 },
599 + [UBI32_CORE2_AHB_RESET] = { 0x3d5c, 1 },
600 + [UBI32_CORE2_AXI_RESET] = { 0x3d5c, 0 },
601 + [GMAC_CORE1_RESET] = { 0x3cbc, 0 },
602 + [GMAC_CORE2_RESET] = { 0x3cdc, 0 },
603 + [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
604 + [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
605 + [GMAC_AHB_RESET] = { 0x3e24, 0 },
606 + [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
607 + [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
608 + [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
609 + [NSS_CH0_HW_RST_RX_125M_N_RESET] = { 0x3b60, 3 },
610 + [NSS_CH0_RST_TX_125M_N_RESET] = { 0x3b60, 4 },
611 + [NSS_CH1_RST_RX_CLK_N_RESET] = { 0x3b60, 5 },
612 + [NSS_CH1_RST_TX_CLK_N_RESET] = { 0x3b60, 6 },
613 + [NSS_CH1_RST_RX_125M_N_RESET] = { 0x3b60, 7 },
614 + [NSS_CH1_HW_RST_RX_125M_N_RESET] = { 0x3b60, 8 },
615 + [NSS_CH1_RST_TX_125M_N_RESET] = { 0x3b60, 9 },
616 + [NSS_CH2_RST_RX_CLK_N_RESET] = { 0x3b60, 10 },
617 + [NSS_CH2_RST_TX_CLK_N_RESET] = { 0x3b60, 11 },
618 + [NSS_CH2_RST_RX_125M_N_RESET] = { 0x3b60, 12 },
619 + [NSS_CH2_HW_RST_RX_125M_N_RESET] = { 0x3b60, 13 },
620 + [NSS_CH2_RST_TX_125M_N_RESET] = { 0x3b60, 14 },
621 + [NSS_CH3_RST_RX_CLK_N_RESET] = { 0x3b60, 15 },
622 + [NSS_CH3_RST_TX_CLK_N_RESET] = { 0x3b60, 16 },
623 + [NSS_CH3_RST_RX_125M_N_RESET] = { 0x3b60, 17 },
624 + [NSS_CH3_HW_RST_RX_125M_N_RESET] = { 0x3b60, 18 },
625 + [NSS_CH3_RST_TX_125M_N_RESET] = { 0x3b60, 19 },
626 + [NSS_RST_RX_250M_125M_N_RESET] = { 0x3b60, 20 },
627 + [NSS_RST_TX_250M_125M_N_RESET] = { 0x3b60, 21 },
628 + [NSS_QSGMII_TXPI_RST_N_RESET] = { 0x3b60, 22 },
629 + [NSS_QSGMII_CDR_RST_N_RESET] = { 0x3b60, 23 },
630 + [NSS_SGMII2_CDR_RST_N_RESET] = { 0x3b60, 24 },
631 + [NSS_SGMII3_CDR_RST_N_RESET] = { 0x3b60, 25 },
632 + [NSS_CAL_PRBS_RST_N_RESET] = { 0x3b60, 26 },
633 + [NSS_LCKDT_RST_N_RESET] = { 0x3b60, 27 },
634 + [NSS_SRDS_N_RESET] = { 0x3b60, 28 },
637 static const struct regmap_config gcc_ipq806x_regmap_config = {
638 @@ -2502,6 +3074,8 @@ static int gcc_ipq806x_probe(struct plat
641 struct device *dev = &pdev->dev;
642 + struct regmap *regmap;
645 /* Temporary until RPM clocks supported */
646 clk = clk_register_fixed_rate(dev, "cxo", NULL, CLK_IS_ROOT, 25000000);
647 @@ -2512,7 +3086,25 @@ static int gcc_ipq806x_probe(struct plat
651 - return qcom_cc_probe(pdev, &gcc_ipq806x_desc);
652 + ret = qcom_cc_probe(pdev, &gcc_ipq806x_desc);
656 + regmap = dev_get_regmap(dev, NULL);
660 + /* Setup PLL18 static bits */
661 + regmap_update_bits(regmap, 0x31a4, 0xffffffc0, 0x40000400);
662 + regmap_write(regmap, 0x31b0, 0x3080);
664 + /* Set GMAC footswitch sleep/wakeup values */
665 + regmap_write(regmap, 0x3cb8, 8);
666 + regmap_write(regmap, 0x3cd8, 8);
667 + regmap_write(regmap, 0x3cf8, 8);
668 + regmap_write(regmap, 0x3d18, 8);
673 static int gcc_ipq806x_remove(struct platform_device *pdev)
674 --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
675 +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
677 #define UBI32_CORE2_CLK_SRC 278
678 #define UBI32_CORE1_CLK 279
679 #define UBI32_CORE2_CLK 280
680 +#define NSSTCM_CLK_SRC 281
681 +#define NSSTCM_CLK 282
684 --- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h
685 +++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
687 #define USB30_1_PHY_RESET 112
688 #define NSSFB0_RESET 113
689 #define NSSFB1_RESET 114
690 +#define UBI32_CORE1_CLKRST_CLAMP_RESET 115
691 +#define UBI32_CORE1_CLAMP_RESET 116
692 +#define UBI32_CORE1_AHB_RESET 117
693 +#define UBI32_CORE1_AXI_RESET 118
694 +#define UBI32_CORE2_CLKRST_CLAMP_RESET 119
695 +#define UBI32_CORE2_CLAMP_RESET 120
696 +#define UBI32_CORE2_AHB_RESET 121
697 +#define UBI32_CORE2_AXI_RESET 122
698 +#define GMAC_CORE1_RESET 123
699 +#define GMAC_CORE2_RESET 124
700 +#define GMAC_CORE3_RESET 125
701 +#define GMAC_CORE4_RESET 126
702 +#define GMAC_AHB_RESET 127
703 +#define NSS_CH0_RST_RX_CLK_N_RESET 128
704 +#define NSS_CH0_RST_TX_CLK_N_RESET 129
705 +#define NSS_CH0_RST_RX_125M_N_RESET 130
706 +#define NSS_CH0_HW_RST_RX_125M_N_RESET 131
707 +#define NSS_CH0_RST_TX_125M_N_RESET 132
708 +#define NSS_CH1_RST_RX_CLK_N_RESET 133
709 +#define NSS_CH1_RST_TX_CLK_N_RESET 134
710 +#define NSS_CH1_RST_RX_125M_N_RESET 135
711 +#define NSS_CH1_HW_RST_RX_125M_N_RESET 136
712 +#define NSS_CH1_RST_TX_125M_N_RESET 137
713 +#define NSS_CH2_RST_RX_CLK_N_RESET 138
714 +#define NSS_CH2_RST_TX_CLK_N_RESET 139
715 +#define NSS_CH2_RST_RX_125M_N_RESET 140
716 +#define NSS_CH2_HW_RST_RX_125M_N_RESET 141
717 +#define NSS_CH2_RST_TX_125M_N_RESET 142
718 +#define NSS_CH3_RST_RX_CLK_N_RESET 143
719 +#define NSS_CH3_RST_TX_CLK_N_RESET 144
720 +#define NSS_CH3_RST_RX_125M_N_RESET 145
721 +#define NSS_CH3_HW_RST_RX_125M_N_RESET 146
722 +#define NSS_CH3_RST_TX_125M_N_RESET 147
723 +#define NSS_RST_RX_250M_125M_N_RESET 148
724 +#define NSS_RST_TX_250M_125M_N_RESET 149
725 +#define NSS_QSGMII_TXPI_RST_N_RESET 150
726 +#define NSS_QSGMII_CDR_RST_N_RESET 151
727 +#define NSS_SGMII2_CDR_RST_N_RESET 152
728 +#define NSS_SGMII3_CDR_RST_N_RESET 153
729 +#define NSS_CAL_PRBS_RST_N_RESET 154
730 +#define NSS_LCKDT_RST_N_RESET 155
731 +#define NSS_SRDS_N_RESET 156