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ipq806x: fix pcie tx0-term-offset setting
[openwrt/staging/chunkeey.git] / target / linux / ipq806x / patches-4.1 / 112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
1 From 5b40516b2f5fb9b2a7d6d3e2e924f12ec9d183a8 Mon Sep 17 00:00:00 2001
2 From: Mathieu Olivari <mathieu@codeaurora.org>
3 Date: Tue, 21 Apr 2015 19:01:42 -0700
4 Subject: [PATCH 8/9] ARM: dts: qcom: add pcie nodes to ipq806x platforms
5
6 qcom-pcie driver now supports version 0 of the controller. This change
7 adds the corresponding entries to the IPQ806x dtsi file and
8 corresponding platform (AP148).
9
10 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
11 ---
12 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 30 ++++++++
13 arch/arm/boot/dts/qcom-ipq8064.dtsi | 124 +++++++++++++++++++++++++++++++
14 2 files changed, 154 insertions(+)
15
16 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
17 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
18 @@ -35,6 +35,24 @@
19 bias-disable;
20 };
21
22 + pcie0_pins: pcie0_pinmux {
23 + mux {
24 + pins = "gpio3";
25 + function = "pcie1_rst";
26 + drive-strength = <12>;
27 + bias-disable;
28 + };
29 + };
30 +
31 + pcie1_pins: pcie1_pinmux {
32 + mux {
33 + pins = "gpio48";
34 + function = "pcie2_rst";
35 + drive-strength = <12>;
36 + bias-disable;
37 + };
38 + };
39 +
40 spi_pins: spi_pins {
41 mux {
42 pins = "gpio18", "gpio19", "gpio21";
43 @@ -91,5 +109,21 @@
44 sata@29000000 {
45 status = "ok";
46 };
47 +
48 + pcie0: pci@1b500000 {
49 + status = "ok";
50 + reset-gpio = <&qcom_pinmux 3 0>;
51 + pinctrl-0 = <&pcie0_pins>;
52 + pinctrl-names = "default";
53 + phy-tx0-term-offset = <7>;
54 + };
55 +
56 + pcie1: pci@1b700000 {
57 + status = "ok";
58 + reset-gpio = <&qcom_pinmux 48 0>;
59 + pinctrl-0 = <&pcie1_pins>;
60 + pinctrl-names = "default";
61 + phy-tx0-term-offset = <7>;
62 + };
63 };
64 };
65 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
66 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
67 @@ -30,6 +30,33 @@
68 bias-disable;
69 };
70
71 + pcie0_pins: pcie0_pinmux {
72 + mux {
73 + pins = "gpio3";
74 + function = "pcie1_rst";
75 + drive-strength = <12>;
76 + bias-disable;
77 + };
78 + };
79 +
80 + pcie1_pins: pcie1_pinmux {
81 + mux {
82 + pins = "gpio48";
83 + function = "pcie2_rst";
84 + drive-strength = <12>;
85 + bias-disable;
86 + };
87 + };
88 +
89 + pcie2_pins: pcie2_pinmux {
90 + mux {
91 + pins = "gpio63";
92 + function = "pcie3_rst";
93 + drive-strength = <12>;
94 + bias-disable;
95 + };
96 + };
97 +
98 spi_pins: spi_pins {
99 mux {
100 pins = "gpio18", "gpio19", "gpio21";
101 @@ -128,5 +155,26 @@
102 usb30@1 {
103 status = "ok";
104 };
105 +
106 + pcie0: pci@1b500000 {
107 + status = "ok";
108 + reset-gpio = <&qcom_pinmux 3 0>;
109 + pinctrl-0 = <&pcie0_pins>;
110 + pinctrl-names = "default";
111 + };
112 +
113 + pcie1: pci@1b700000 {
114 + status = "ok";
115 + reset-gpio = <&qcom_pinmux 48 0>;
116 + pinctrl-0 = <&pcie1_pins>;
117 + pinctrl-names = "default";
118 + };
119 +
120 + pcie2: pci@1b900000 {
121 + status = "ok";
122 + reset-gpio = <&qcom_pinmux 63 0>;
123 + pinctrl-0 = <&pcie2_pins>;
124 + pinctrl-names = "default";
125 + };
126 };
127 };
128 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
129 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
130 @@ -4,6 +4,8 @@
131 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
132 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
133 #include <dt-bindings/soc/qcom,gsbi.h>
134 +#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
135 +#include <dt-bindings/interrupt-controller/arm-gic.h>
136
137 / {
138 model = "Qualcomm IPQ8064";
139 @@ -333,6 +335,129 @@
140 compatible = "syscon";
141 reg = <0x01200600 0x100>;
142 };
143 +
144 + pcie0: pci@1b500000 {
145 + compatible = "qcom,pcie-v0";
146 + reg = <0x1b500000 0x1000
147 + 0x1b502000 0x80
148 + 0x1b600000 0x100
149 + 0x0ff00000 0x100000>;
150 + reg-names = "dbi", "elbi", "parf", "config";
151 + device_type = "pci";
152 + linux,pci-domain = <0>;
153 + bus-range = <0x00 0xff>;
154 + num-lanes = <1>;
155 + #address-cells = <3>;
156 + #size-cells = <2>;
157 +
158 + ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
159 + 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
160 +
161 + interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
162 + interrupt-names = "msi";
163 + #interrupt-cells = <1>;
164 + interrupt-map-mask = <0 0 0 0x7>;
165 + interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
166 + <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
167 + <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
168 + <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
169 +
170 + clocks = <&gcc PCIE_A_CLK>,
171 + <&gcc PCIE_H_CLK>,
172 + <&gcc PCIE_PHY_CLK>;
173 + clock-names = "core", "iface", "phy";
174 +
175 + resets = <&gcc PCIE_ACLK_RESET>,
176 + <&gcc PCIE_HCLK_RESET>,
177 + <&gcc PCIE_POR_RESET>,
178 + <&gcc PCIE_PCI_RESET>,
179 + <&gcc PCIE_PHY_RESET>;
180 + reset-names = "axi", "ahb", "por", "pci", "phy";
181 +
182 + status = "disabled";
183 + };
184 +
185 + pcie1: pci@1b700000 {
186 + compatible = "qcom,pcie-v0";
187 + reg = <0x1b700000 0x1000
188 + 0x1b702000 0x80
189 + 0x1b800000 0x100
190 + 0x31f00000 0x100000>;
191 + reg-names = "dbi", "elbi", "parf", "config";
192 + device_type = "pci";
193 + linux,pci-domain = <1>;
194 + bus-range = <0x00 0xff>;
195 + num-lanes = <1>;
196 + #address-cells = <3>;
197 + #size-cells = <2>;
198 +
199 + ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
200 + 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
201 +
202 + interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
203 + interrupt-names = "msi";
204 + #interrupt-cells = <1>;
205 + interrupt-map-mask = <0 0 0 0x7>;
206 + interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
207 + <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
208 + <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
209 + <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
210 +
211 + clocks = <&gcc PCIE_1_A_CLK>,
212 + <&gcc PCIE_1_H_CLK>,
213 + <&gcc PCIE_1_PHY_CLK>;
214 + clock-names = "core", "iface", "phy";
215 +
216 + resets = <&gcc PCIE_1_ACLK_RESET>,
217 + <&gcc PCIE_1_HCLK_RESET>,
218 + <&gcc PCIE_1_POR_RESET>,
219 + <&gcc PCIE_1_PCI_RESET>,
220 + <&gcc PCIE_1_PHY_RESET>;
221 + reset-names = "axi", "ahb", "por", "pci", "phy";
222 +
223 + status = "disabled";
224 + };
225 +
226 + pcie2: pci@1b900000 {
227 + compatible = "qcom,pcie-v0";
228 + reg = <0x1b900000 0x1000
229 + 0x1b902000 0x80
230 + 0x1ba00000 0x100
231 + 0x35f00000 0x100000>;
232 + reg-names = "dbi", "elbi", "parf", "config";
233 + device_type = "pci";
234 + linux,pci-domain = <2>;
235 + bus-range = <0x00 0xff>;
236 + num-lanes = <1>;
237 + #address-cells = <3>;
238 + #size-cells = <2>;
239 +
240 + ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
241 + 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
242 +
243 + interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
244 + interrupt-names = "msi";
245 + #interrupt-cells = <1>;
246 + interrupt-map-mask = <0 0 0 0x7>;
247 + interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
248 + <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
249 + <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
250 + <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
251 +
252 + clocks = <&gcc PCIE_2_A_CLK>,
253 + <&gcc PCIE_2_H_CLK>,
254 + <&gcc PCIE_2_PHY_CLK>;
255 + clock-names = "core", "iface", "phy";
256 +
257 + resets = <&gcc PCIE_2_ACLK_RESET>,
258 + <&gcc PCIE_2_HCLK_RESET>,
259 + <&gcc PCIE_2_POR_RESET>,
260 + <&gcc PCIE_2_PCI_RESET>,
261 + <&gcc PCIE_2_PHY_RESET>;
262 + reset-names = "axi", "ahb", "por", "pci", "phy";
263 +
264 + status = "disabled";
265 + };
266 };
267
268 sfpb_mutex: sfpb-mutex {
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