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4 Subject: [v3,5/5] arm: qcom: dts: Enable NAND node on IPQ8064 AP148 platform
5 From: Archit Taneja <architt@codeaurora.org>
6 X-Patchwork-Id: 6927091
7 Message-Id: <1438578498-32254-6-git-send-email-architt@codeaurora.org>
8 To: linux-mtd@lists.infradead.org, dehrenberg@google.com,
9 cernekee@gmail.com, computersforpeace@gmail.com
10 Cc: linux-arm-msm@vger.kernel.org, agross@codeaurora.org,
11 sboyd@codeaurora.org, linux-kernel@vger.kernel.org,
12 Archit Taneja <architt@codeaurora.org>, devicetree@vger.kernel.org
13 Date: Mon, 3 Aug 2015 10:38:18 +0530
15 Enable the NAND controller node on the AP148 platform. Provide pinmux
18 Cc: devicetree@vger.kernel.org
20 Signed-off-by: Archit Taneja <architt@codeaurora.org>
23 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 36 ++++++++++++++++++++++++++++++++
24 1 file changed, 36 insertions(+)
26 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
27 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
32 + nand_pins: nand_pins {
34 + pins = "gpio34", "gpio35", "gpio36",
35 + "gpio37", "gpio38", "gpio39",
36 + "gpio40", "gpio41", "gpio42",
37 + "gpio43", "gpio44", "gpio45",
40 + drive-strength = <10>;
48 + pins = "gpio40", "gpio41", "gpio42",
49 + "gpio43", "gpio44", "gpio45",
59 phy-tx0-term-offset = <7>;
65 + pinctrl-0 = <&nand_pins>;
66 + pinctrl-names = "default";
68 + nand-ecc-strength = <4>;
69 + nand-bus-width = <8>;