1 From cab1f4720e82f2e17eaeed9a9ad9e4f07c742977 Mon Sep 17 00:00:00 2001
2 From: Mathieu Olivari <mathieu@codeaurora.org>
3 Date: Mon, 11 May 2015 12:29:18 -0700
4 Subject: [PATCH 8/8] ARM: dts: qcom: add gmac nodes to ipq806x platforms
6 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
8 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 31 ++++++++++++
9 arch/arm/boot/dts/qcom-ipq8064-db149.dts | 43 ++++++++++++++++
10 arch/arm/boot/dts/qcom-ipq8064.dtsi | 86 ++++++++++++++++++++++++++++++++
11 3 files changed, 160 insertions(+)
13 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
14 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
20 + rgmii2_pins: rgmii2_pins {
22 + pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32",
23 + "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62" ;
24 + function = "rgmii2";
25 + drive-strength = <8>;
37 + gmac1: ethernet@37200000 {
40 + phy-handle = <&phy4>;
43 + pinctrl-0 = <&rgmii2_pins>;
44 + pinctrl-names = "default";
47 + gmac2: ethernet@37400000 {
59 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
60 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
66 + rgmii0_pins: rgmii0_pins {
68 + pins = "gpio2", "gpio66";
69 + drive-strength = <8>;
75 gsbi2: gsbi@12480000 {
81 + gmac0: ethernet@37000000 {
85 + phy-handle = <&phy4>;
87 + pinctrl-0 = <&rgmii0_pins>;
88 + pinctrl-names = "default";
91 + gmac1: ethernet@37200000 {
102 + gmac2: ethernet@37400000 {
104 + phy-mode = "sgmii";
106 + phy-handle = <&phy6>;
109 + gmac3: ethernet@37600000 {
111 + phy-mode = "sgmii";
113 + phy-handle = <&phy7>;
117 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
118 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
123 + nss_common: syscon@03000000 {
124 + compatible = "syscon";
125 + reg = <0x03000000 0x0000FFFF>;
128 + qsgmii_csr: syscon@1bb00000 {
129 + compatible = "syscon";
130 + reg = <0x1bb00000 0x000001FF>;
133 + gmac0: ethernet@37000000 {
134 + device_type = "network";
135 + compatible = "qcom,ipq806x-gmac";
136 + reg = <0x37000000 0x200000>;
137 + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
138 + interrupt-names = "macirq";
140 + qcom,nss-common = <&nss_common>;
141 + qcom,qsgmii-csr = <&qsgmii_csr>;
143 + clocks = <&gcc GMAC_CORE1_CLK>;
144 + clock-names = "stmmaceth";
146 + resets = <&gcc GMAC_CORE1_RESET>;
147 + reset-names = "stmmaceth";
149 + status = "disabled";
152 + gmac1: ethernet@37200000 {
153 + device_type = "network";
154 + compatible = "qcom,ipq806x-gmac";
155 + reg = <0x37200000 0x200000>;
156 + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
157 + interrupt-names = "macirq";
159 + qcom,nss-common = <&nss_common>;
160 + qcom,qsgmii-csr = <&qsgmii_csr>;
162 + clocks = <&gcc GMAC_CORE2_CLK>;
163 + clock-names = "stmmaceth";
165 + resets = <&gcc GMAC_CORE2_RESET>;
166 + reset-names = "stmmaceth";
168 + status = "disabled";
171 + gmac2: ethernet@37400000 {
172 + device_type = "network";
173 + compatible = "qcom,ipq806x-gmac";
174 + reg = <0x37400000 0x200000>;
175 + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
176 + interrupt-names = "macirq";
178 + qcom,nss-common = <&nss_common>;
179 + qcom,qsgmii-csr = <&qsgmii_csr>;
181 + clocks = <&gcc GMAC_CORE3_CLK>;
182 + clock-names = "stmmaceth";
184 + resets = <&gcc GMAC_CORE3_RESET>;
185 + reset-names = "stmmaceth";
187 + status = "disabled";
190 + gmac3: ethernet@37600000 {
191 + device_type = "network";
192 + compatible = "qcom,ipq806x-gmac";
193 + reg = <0x37600000 0x200000>;
194 + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
195 + interrupt-names = "macirq";
197 + qcom,nss-common = <&nss_common>;
198 + qcom,qsgmii-csr = <&qsgmii_csr>;
200 + clocks = <&gcc GMAC_CORE4_CLK>;
201 + clock-names = "stmmaceth";
203 + resets = <&gcc GMAC_CORE4_RESET>;
204 + reset-names = "stmmaceth";
206 + status = "disabled";