1 From patchwork Fri Dec 8 09:42:22 2017
2 Content-Type: text/plain; charset="utf-8"
4 Content-Transfer-Encoding: 7bit
5 Subject: [v4,04/12] clk: qcom: Add HFPLL driver
6 From: Sricharan R <sricharan@codeaurora.org>
7 X-Patchwork-Id: 10102079
8 Message-Id: <1512726150-7204-5-git-send-email-sricharan@codeaurora.org>
9 To: mturquette@baylibre.com, sboyd@codeaurora.org,
10 devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
11 linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
12 viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
13 Cc: sricharan@codeaurora.org
14 Date: Fri, 8 Dec 2017 15:12:22 +0530
16 From: Stephen Boyd <sboyd@codeaurora.org>
18 On some devices (MSM8974 for example), the HFPLLs are
19 instantiated within the Krait processor subsystem as separate
20 register regions. Add a driver for these PLLs so that we can
21 provide HFPLL clocks for use by the system.
23 Cc: <devicetree@vger.kernel.org>
24 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
26 .../devicetree/bindings/clock/qcom,hfpll.txt | 40 ++++++++
27 drivers/clk/qcom/Kconfig | 8 ++
28 drivers/clk/qcom/Makefile | 1 +
29 drivers/clk/qcom/hfpll.c | 106 +++++++++++++++++++++
30 4 files changed, 155 insertions(+)
31 create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
32 create mode 100644 drivers/clk/qcom/hfpll.c
35 +++ b/Documentation/devicetree/bindings/clock/qcom,hfpll.txt
37 +High-Frequency PLL (HFPLL)
43 + Value type: <string>
44 + Definition: must be "qcom,hfpll"
48 + Value type: <prop-encoded-array>
49 + Definition: address and size of HPLL registers. An optional second
50 + element specifies the address and size of the alias
53 +- clock-output-names:
55 + Value type: <string>
56 + Definition: Name of the PLL. Typically hfpllX where X is a CPU number
57 + starting at 0. Otherwise hfpll_Y where Y is more specific
62 +1) An HFPLL for the L2 cache.
64 + clock-controller@f9016000 {
65 + compatible = "qcom,hfpll";
66 + reg = <0xf9016000 0x30>;
67 + clock-output-names = "hfpll_l2";
70 +2) An HFPLL for CPU0. This HFPLL has the alias register region.
72 + clock-controller@f908a000 {
73 + compatible = "qcom,hfpll";
74 + reg = <0xf908a000 0x30>, <0xf900a000 0x30>;
75 + clock-output-names = "hfpll0";
77 --- a/drivers/clk/qcom/Kconfig
78 +++ b/drivers/clk/qcom/Kconfig
79 @@ -196,3 +196,11 @@ config MSM_MMCC_8996
80 Support for the multimedia clock controller on msm8996 devices.
81 Say Y if you want to support multimedia devices such as display,
82 graphics, video encode/decode, camera, etc.
85 + tristate "High-Frequency PLL (HFPLL) Clock Controller"
86 + depends on COMMON_CLK_QCOM
88 + Support for the high-frequency PLLs present on Qualcomm devices.
89 + Say Y if you want to support CPU frequency scaling on devices
90 + such as MSM8974, APQ8084, etc.
91 --- a/drivers/clk/qcom/Makefile
92 +++ b/drivers/clk/qcom/Makefile
93 @@ -35,3 +35,4 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8
94 obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
95 obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
96 obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
97 +obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
99 +++ b/drivers/clk/qcom/hfpll.c
102 + * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
104 + * This program is free software; you can redistribute it and/or modify
105 + * it under the terms of the GNU General Public License version 2 and
106 + * only version 2 as published by the Free Software Foundation.
108 + * This program is distributed in the hope that it will be useful,
109 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
110 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
111 + * GNU General Public License for more details.
114 +#include <linux/kernel.h>
115 +#include <linux/init.h>
116 +#include <linux/module.h>
117 +#include <linux/platform_device.h>
118 +#include <linux/of.h>
119 +#include <linux/clk.h>
120 +#include <linux/clk-provider.h>
121 +#include <linux/regmap.h>
123 +#include "clk-regmap.h"
124 +#include "clk-hfpll.h"
126 +static const struct hfpll_data hdata = {
132 + .config_reg = 0x14,
133 + .config_val = 0x430405d,
134 + .status_reg = 0x1c,
138 + .user_vco_mask = 0x100000,
139 + .low_vco_max_rate = 1248000000,
140 + .min_rate = 537600000UL,
141 + .max_rate = 2900000000UL,
144 +static const struct of_device_id qcom_hfpll_match_table[] = {
145 + { .compatible = "qcom,hfpll" },
148 +MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
150 +static const struct regmap_config hfpll_regmap_config = {
154 + .max_register = 0x30,
158 +static int qcom_hfpll_probe(struct platform_device *pdev)
160 + struct resource *res;
161 + struct device *dev = &pdev->dev;
162 + void __iomem *base;
163 + struct regmap *regmap;
164 + struct clk_hfpll *h;
165 + struct clk_init_data init = {
166 + .parent_names = (const char *[]){ "xo" },
168 + .ops = &clk_ops_hfpll,
171 + h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
175 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
176 + base = devm_ioremap_resource(dev, res);
178 + return PTR_ERR(base);
180 + regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config);
181 + if (IS_ERR(regmap))
182 + return PTR_ERR(regmap);
184 + if (of_property_read_string_index(dev->of_node, "clock-output-names",
189 + h->clkr.hw.init = &init;
190 + spin_lock_init(&h->lock);
192 + return devm_clk_register_regmap(&pdev->dev, &h->clkr);
195 +static struct platform_driver qcom_hfpll_driver = {
196 + .probe = qcom_hfpll_probe,
198 + .name = "qcom-hfpll",
199 + .of_match_table = qcom_hfpll_match_table,
202 +module_platform_driver(qcom_hfpll_driver);
204 +MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
205 +MODULE_LICENSE("GPL v2");
206 +MODULE_ALIAS("platform:qcom-hfpll");