target/linux/ipq806x/patches-4.19/0034-0006-clk-qcom-Add-IPQ806X-s-HFPLLs.patch

   1 From 1f79131bfd512f322c16b58dca581ce39beafab9 Mon Sep 17 00:00:00 2001
   2 From: Stephen Boyd <sboyd@codeaurora.org>
   3 Date: Tue, 14 Aug 2018 17:42:25 +0530
   4 Subject: [PATCH 06/12] clk: qcom: Add IPQ806X's HFPLLs
   5
   6 Describe the HFPLLs present on IPQ806X devices.
   7
   8 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
   9 Signed-off-by: Sricharan R <sricharan@codeaurora.org>
  10 Tested-by: Craig Tatlor <ctatlor97@gmail.com>
  11 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  12 ---
  13  drivers/clk/qcom/gcc-ipq806x.c | 82 ++++++++++++++++++++++++++++++++++
  14  1 file changed, 82 insertions(+)
  15
  16 --- a/drivers/clk/qcom/gcc-ipq806x.c
  17 +++ b/drivers/clk/qcom/gcc-ipq806x.c
  18 @@ -30,6 +30,7 @@
  19  #include "clk-pll.h"
  20  #include "clk-rcg.h"
  21  #include "clk-branch.h"
  22 +#include "clk-hfpll.h"
  23  #include "reset.h"
  24
  25  static struct clk_pll pll0 = {
  26 @@ -113,6 +114,84 @@ static struct clk_regmap pll8_vote = {
  27         },
  28  };
  29
  30 +static struct hfpll_data hfpll0_data = {
  31 +       .mode_reg = 0x3200,
  32 +       .l_reg = 0x3208,
  33 +       .m_reg = 0x320c,
  34 +       .n_reg = 0x3210,
  35 +       .config_reg = 0x3204,
  36 +       .status_reg = 0x321c,
  37 +       .config_val = 0x7845c665,
  38 +       .droop_reg = 0x3214,
  39 +       .droop_val = 0x0108c000,
  40 +       .min_rate = 600000000UL,
  41 +       .max_rate = 1800000000UL,
  42 +};
  43 +
  44 +static struct clk_hfpll hfpll0 = {
  45 +       .d = &hfpll0_data,
  46 +       .clkr.hw.init = &(struct clk_init_data){
  47 +               .parent_names = (const char *[]){ "pxo" },
  48 +               .num_parents = 1,
  49 +               .name = "hfpll0",
  50 +               .ops = &clk_ops_hfpll,
  51 +               .flags = CLK_IGNORE_UNUSED,
  52 +       },
  53 +       .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
  54 +};
  55 +
  56 +static struct hfpll_data hfpll1_data = {
  57 +       .mode_reg = 0x3240,
  58 +       .l_reg = 0x3248,
  59 +       .m_reg = 0x324c,
  60 +       .n_reg = 0x3250,
  61 +       .config_reg = 0x3244,
  62 +       .status_reg = 0x325c,
  63 +       .config_val = 0x7845c665,
  64 +       .droop_reg = 0x3314,
  65 +       .droop_val = 0x0108c000,
  66 +       .min_rate = 600000000UL,
  67 +       .max_rate = 1800000000UL,
  68 +};
  69 +
  70 +static struct clk_hfpll hfpll1 = {
  71 +       .d = &hfpll1_data,
  72 +       .clkr.hw.init = &(struct clk_init_data){
  73 +               .parent_names = (const char *[]){ "pxo" },
  74 +               .num_parents = 1,
  75 +               .name = "hfpll1",
  76 +               .ops = &clk_ops_hfpll,
  77 +               .flags = CLK_IGNORE_UNUSED,
  78 +       },
  79 +       .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
  80 +};
  81 +
  82 +static struct hfpll_data hfpll_l2_data = {
  83 +       .mode_reg = 0x3300,
  84 +       .l_reg = 0x3308,
  85 +       .m_reg = 0x330c,
  86 +       .n_reg = 0x3310,
  87 +       .config_reg = 0x3304,
  88 +       .status_reg = 0x331c,
  89 +       .config_val = 0x7845c665,
  90 +       .droop_reg = 0x3314,
  91 +       .droop_val = 0x0108c000,
  92 +       .min_rate = 600000000UL,
  93 +       .max_rate = 1800000000UL,
  94 +};
  95 +
  96 +static struct clk_hfpll hfpll_l2 = {
  97 +       .d = &hfpll_l2_data,
  98 +       .clkr.hw.init = &(struct clk_init_data){
  99 +               .parent_names = (const char *[]){ "pxo" },
 100 +               .num_parents = 1,
 101 +               .name = "hfpll_l2",
 102 +               .ops = &clk_ops_hfpll,
 103 +               .flags = CLK_IGNORE_UNUSED,
 104 +       },
 105 +       .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
 106 +};
 107 +
 108  static struct clk_pll pll14 = {
 109         .l_reg = 0x31c4,
 110         .m_reg = 0x31c8,
 111 @@ -2798,6 +2877,9 @@ static struct clk_regmap *gcc_ipq806x_cl
 112         [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
 113         [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
 114         [NSSTCM_CLK] = &nss_tcm_clk.clkr,
 115 +       [PLL9] = &hfpll0.clkr,
 116 +       [PLL10] = &hfpll1.clkr,
 117 +       [PLL12] = &hfpll_l2.clkr,
 118  };
 119
 120  static const struct qcom_reset_map gcc_ipq806x_resets[] = {