1 From 4d7dc77babfef1d6cb8fd825e2f17dc3384c3272 Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Tue, 14 Aug 2018 17:42:26 +0530
4 Subject: [PATCH 07/12] clk: qcom: Add support for Krait clocks
6 The Krait clocks are made up of a series of muxes and a divider
7 that choose between a fixed rate clock and dedicated HFPLLs for
8 each CPU. Instead of using mmio accesses to remux parents, the
9 Krait implementation exposes the remux control via cp15
10 registers. Support these clocks.
12 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
13 Signed-off-by: Sricharan R <sricharan@codeaurora.org>
14 Tested-by: Craig Tatlor <ctatlor97@gmail.com>
15 [sboyd@kernel.org: Move hidden config to top outside of the visible qcom
16 config zone so that menuconfig looks nice]
17 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
19 drivers/clk/qcom/Kconfig | 4 ++
20 drivers/clk/qcom/Makefile | 1 +
21 drivers/clk/qcom/clk-krait.c | 124 +++++++++++++++++++++++++++++++++++
22 drivers/clk/qcom/clk-krait.h | 37 +++++++++++
23 4 files changed, 166 insertions(+)
24 create mode 100644 drivers/clk/qcom/clk-krait.c
25 create mode 100644 drivers/clk/qcom/clk-krait.h
27 --- a/drivers/clk/qcom/Kconfig
28 +++ b/drivers/clk/qcom/Kconfig
32 + select KRAIT_L2_ACCESSORS
36 select PM_GENERIC_DOMAINS if PM
37 --- a/drivers/clk/qcom/Makefile
38 +++ b/drivers/clk/qcom/Makefile
39 @@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o
40 clk-qcom-y += clk-regmap-divider.o
41 clk-qcom-y += clk-regmap-mux.o
42 clk-qcom-y += clk-regmap-mux-div.o
43 +clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
44 clk-qcom-y += clk-hfpll.o
46 clk-qcom-$(CONFIG_QCOM_GDSC) += gdsc.o
48 +++ b/drivers/clk/qcom/clk-krait.c
50 +// SPDX-License-Identifier: GPL-2.0
51 +// Copyright (c) 2018, The Linux Foundation. All rights reserved.
53 +#include <linux/kernel.h>
54 +#include <linux/module.h>
55 +#include <linux/init.h>
56 +#include <linux/io.h>
57 +#include <linux/delay.h>
58 +#include <linux/err.h>
59 +#include <linux/clk-provider.h>
60 +#include <linux/spinlock.h>
62 +#include <asm/krait-l2-accessors.h>
64 +#include "clk-krait.h"
66 +/* Secondary and primary muxes share the same cp15 register */
67 +static DEFINE_SPINLOCK(krait_clock_reg_lock);
70 +static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel)
72 + unsigned long flags;
75 + spin_lock_irqsave(&krait_clock_reg_lock, flags);
76 + regval = krait_get_l2_indirect_reg(mux->offset);
77 + regval &= ~(mux->mask << mux->shift);
78 + regval |= (sel & mux->mask) << mux->shift;
80 + regval &= ~(mux->mask << (mux->shift + LPL_SHIFT));
81 + regval |= (sel & mux->mask) << (mux->shift + LPL_SHIFT);
83 + krait_set_l2_indirect_reg(mux->offset, regval);
84 + spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
86 + /* Wait for switch to complete. */
91 +static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
93 + struct krait_mux_clk *mux = to_krait_mux_clk(hw);
96 + sel = clk_mux_reindex(index, mux->parent_map, 0);
98 + /* Don't touch mux if CPU is off as it won't work */
99 + if (__clk_is_enabled(hw->clk))
100 + __krait_mux_set_sel(mux, sel);
105 +static u8 krait_mux_get_parent(struct clk_hw *hw)
107 + struct krait_mux_clk *mux = to_krait_mux_clk(hw);
110 + sel = krait_get_l2_indirect_reg(mux->offset);
111 + sel >>= mux->shift;
113 + mux->en_mask = sel;
115 + return clk_mux_get_parent(hw, sel, mux->parent_map, 0);
118 +const struct clk_ops krait_mux_clk_ops = {
119 + .set_parent = krait_mux_set_parent,
120 + .get_parent = krait_mux_get_parent,
121 + .determine_rate = __clk_mux_determine_rate_closest,
123 +EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
125 +/* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
126 +static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
127 + unsigned long *parent_rate)
129 + *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
130 + return DIV_ROUND_UP(*parent_rate, 2);
133 +static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
134 + unsigned long parent_rate)
136 + struct krait_div2_clk *d = to_krait_div2_clk(hw);
137 + unsigned long flags;
139 + u32 mask = BIT(d->width) - 1;
142 + mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
144 + spin_lock_irqsave(&krait_clock_reg_lock, flags);
145 + val = krait_get_l2_indirect_reg(d->offset);
147 + krait_set_l2_indirect_reg(d->offset, val);
148 + spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
153 +static unsigned long
154 +krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
156 + struct krait_div2_clk *d = to_krait_div2_clk(hw);
157 + u32 mask = BIT(d->width) - 1;
160 + div = krait_get_l2_indirect_reg(d->offset);
163 + div = (div + 1) * 2;
165 + return DIV_ROUND_UP(parent_rate, div);
168 +const struct clk_ops krait_div2_clk_ops = {
169 + .round_rate = krait_div2_round_rate,
170 + .set_rate = krait_div2_set_rate,
171 + .recalc_rate = krait_div2_recalc_rate,
173 +EXPORT_SYMBOL_GPL(krait_div2_clk_ops);
175 +++ b/drivers/clk/qcom/clk-krait.h
177 +/* SPDX-License-Identifier: GPL-2.0 */
179 +#ifndef __QCOM_CLK_KRAIT_H
180 +#define __QCOM_CLK_KRAIT_H
182 +#include <linux/clk-provider.h>
184 +struct krait_mux_clk {
185 + unsigned int *parent_map;
193 + struct notifier_block clk_nb;
196 +#define to_krait_mux_clk(_hw) container_of(_hw, struct krait_mux_clk, hw)
198 +extern const struct clk_ops krait_mux_clk_ops;
200 +struct krait_div2_clk {
209 +#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw)
211 +extern const struct clk_ops krait_div2_clk_ops;