1 From 5b40516b2f5fb9b2a7d6d3e2e924f12ec9d183a8 Mon Sep 17 00:00:00 2001
2 From: Mathieu Olivari <mathieu@codeaurora.org>
3 Date: Tue, 21 Apr 2015 19:01:42 -0700
4 Subject: [PATCH 8/9] ARM: dts: qcom: add pcie nodes to ipq806x platforms
6 qcom-pcie driver now supports version 0 of the controller. This change
7 adds the corresponding entries to the IPQ806x dtsi file and
8 corresponding platform (AP148).
10 Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
12 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 30 ++++++++
13 arch/arm/boot/dts/qcom-ipq8064.dtsi | 124 +++++++++++++++++++++++++++++++
14 2 files changed, 154 insertions(+)
16 --- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
17 +++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
23 + pcie0: pci@1b500000 {
25 + phy-tx0-term-offset = <7>;
28 + pcie1: pci@1b700000 {
30 + phy-tx0-term-offset = <7>;
34 --- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
35 +++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
41 + pcie0: pci@1b500000 {
45 + pcie1: pci@1b700000 {
49 + pcie2: pci@1b900000 {
54 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
55 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
57 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
58 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
59 #include <dt-bindings/soc/qcom,gsbi.h>
60 +#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
61 +#include <dt-bindings/interrupt-controller/arm-gic.h>
62 +#include <dt-bindings/gpio/gpio.h>
65 model = "Qualcomm IPQ8064";
68 #interrupt-cells = <2>;
69 interrupts = <0 16 0x4>;
71 + pcie0_pins: pcie0_pinmux {
74 + function = "pcie1_rst";
75 + drive-strength = <2>;
80 + pcie1_pins: pcie1_pinmux {
83 + function = "pcie2_rst";
84 + drive-strength = <2>;
89 + pcie2_pins: pcie2_pinmux {
92 + function = "pcie3_rst";
93 + drive-strength = <2>;
100 intc: interrupt-controller@2000000 {
101 @@ -415,6 +446,144 @@
106 + pcie0: pci@1b500000 {
107 + compatible = "qcom,pcie-v0";
108 + reg = <0x1b500000 0x1000
111 + 0x0ff00000 0x100000>;
112 + reg-names = "dbi", "elbi", "parf", "config";
113 + device_type = "pci";
114 + linux,pci-domain = <0>;
115 + bus-range = <0x00 0xff>;
117 + #address-cells = <3>;
120 + ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
121 + 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
123 + interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
124 + interrupt-names = "msi";
125 + #interrupt-cells = <1>;
126 + interrupt-map-mask = <0 0 0 0x7>;
127 + interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
128 + <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
129 + <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
130 + <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
132 + clocks = <&gcc PCIE_A_CLK>,
134 + <&gcc PCIE_PHY_CLK>;
135 + clock-names = "core", "iface", "phy";
137 + resets = <&gcc PCIE_ACLK_RESET>,
138 + <&gcc PCIE_HCLK_RESET>,
139 + <&gcc PCIE_POR_RESET>,
140 + <&gcc PCIE_PCI_RESET>,
141 + <&gcc PCIE_PHY_RESET>;
142 + reset-names = "axi", "ahb", "por", "pci", "phy";
144 + pinctrl-0 = <&pcie0_pins>;
145 + pinctrl-names = "default";
147 + perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
149 + status = "disabled";
152 + pcie1: pci@1b700000 {
153 + compatible = "qcom,pcie-v0";
154 + reg = <0x1b700000 0x1000
157 + 0x31f00000 0x100000>;
158 + reg-names = "dbi", "elbi", "parf", "config";
159 + device_type = "pci";
160 + linux,pci-domain = <1>;
161 + bus-range = <0x00 0xff>;
163 + #address-cells = <3>;
166 + ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
167 + 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
169 + interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
170 + interrupt-names = "msi";
171 + #interrupt-cells = <1>;
172 + interrupt-map-mask = <0 0 0 0x7>;
173 + interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
174 + <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
175 + <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
176 + <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
178 + clocks = <&gcc PCIE_1_A_CLK>,
179 + <&gcc PCIE_1_H_CLK>,
180 + <&gcc PCIE_1_PHY_CLK>;
181 + clock-names = "core", "iface", "phy";
183 + resets = <&gcc PCIE_1_ACLK_RESET>,
184 + <&gcc PCIE_1_HCLK_RESET>,
185 + <&gcc PCIE_1_POR_RESET>,
186 + <&gcc PCIE_1_PCI_RESET>,
187 + <&gcc PCIE_1_PHY_RESET>;
188 + reset-names = "axi", "ahb", "por", "pci", "phy";
190 + pinctrl-0 = <&pcie1_pins>;
191 + pinctrl-names = "default";
193 + perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
195 + status = "disabled";
198 + pcie2: pci@1b900000 {
199 + compatible = "qcom,pcie-v0";
200 + reg = <0x1b900000 0x1000
203 + 0x35f00000 0x100000>;
204 + reg-names = "dbi", "elbi", "parf", "config";
205 + device_type = "pci";
206 + linux,pci-domain = <2>;
207 + bus-range = <0x00 0xff>;
209 + #address-cells = <3>;
212 + ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
213 + 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
215 + interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
216 + interrupt-names = "msi";
217 + #interrupt-cells = <1>;
218 + interrupt-map-mask = <0 0 0 0x7>;
219 + interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
220 + <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
221 + <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
222 + <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
224 + clocks = <&gcc PCIE_2_A_CLK>,
225 + <&gcc PCIE_2_H_CLK>,
226 + <&gcc PCIE_2_PHY_CLK>;
227 + clock-names = "core", "iface", "phy";
229 + resets = <&gcc PCIE_2_ACLK_RESET>,
230 + <&gcc PCIE_2_HCLK_RESET>,
231 + <&gcc PCIE_2_POR_RESET>,
232 + <&gcc PCIE_2_PCI_RESET>,
233 + <&gcc PCIE_2_PHY_RESET>;
234 + reset-names = "axi", "ahb", "por", "pci", "phy";
236 + pinctrl-0 = <&pcie2_pins>;
237 + pinctrl-names = "default";
239 + perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
241 + status = "disabled";
245 sfpb_mutex: sfpb-mutex {