1 From 4c28a15ea536281c8d619e5c6716ade914c79a6e Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Fri, 20 Mar 2015 23:45:21 -0700
4 Subject: [PATCH 1/2] clk: mux: Split out register accessors for reuse
6 We want to reuse the logic in clk-mux.c for other clock drivers
7 that don't use readl as register accessors. Fortunately, there
8 really isn't much to the mux code besides the table indirection
9 and quirk flags if you assume any bit shifting and masking has
10 been done already. Pull that logic out into reusable functions
11 that operate on an optional table and some flags so that other
12 drivers can use the same logic.
14 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
15 Signed-off-by: Ram Chandra Jangir <rjangi@codeaurora.org>
17 drivers/clk/clk-mux.c | 74 +++++++++++++++++++++++++++-----------------
18 include/linux/clk-provider.h | 9 ++++--
19 2 files changed, 53 insertions(+), 30 deletions(-)
21 diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
22 index 7129c86..b03a34d 100644
23 --- a/drivers/clk/clk-mux.c
24 +++ b/drivers/clk/clk-mux.c
27 #define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
29 -static u8 clk_mux_get_parent(struct clk_hw *hw)
30 +unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
31 + unsigned int *table, unsigned long flags)
33 - struct clk_mux *mux = to_clk_mux(hw);
34 int num_parents = clk_hw_get_num_parents(hw);
38 - * FIXME need a mux-specific flag to determine if val is bitwise or numeric
39 - * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
40 - * to 0x7 (index starts at one)
41 - * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
42 - * val = 0x4 really means "bit 2, index starts at bit 0"
44 - val = clk_readl(mux->reg) >> mux->shift;
51 for (i = 0; i < num_parents; i++)
52 - if (mux->table[i] == val)
53 + if (table[i] == val)
58 - if (val && (mux->flags & CLK_MUX_INDEX_BIT))
59 + if (val && (flags & CLK_MUX_INDEX_BIT))
62 - if (val && (mux->flags & CLK_MUX_INDEX_ONE))
63 + if (val && (flags & CLK_MUX_INDEX_ONE))
66 if (val >= num_parents)
67 @@ -64,24 +53,53 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
71 +EXPORT_SYMBOL_GPL(clk_mux_get_parent);
73 -static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
74 +static u8 _clk_mux_get_parent(struct clk_hw *hw)
76 struct clk_mux *mux = to_clk_mux(hw);
78 - unsigned long flags = 0;
81 - index = mux->table[index];
83 + * FIXME need a mux-specific flag to determine if val is bitwise or numeric
84 + * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
85 + * to 0x7 (index starts at one)
86 + * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
87 + * val = 0x4 really means "bit 2, index starts at bit 0"
89 + val = clk_readl(mux->reg) >> mux->shift;
93 - if (mux->flags & CLK_MUX_INDEX_BIT)
95 + return clk_mux_get_parent(hw, val, mux->table, mux->flags);
98 +unsigned int clk_mux_reindex(u8 index, unsigned int *table,
99 + unsigned long flags)
101 + unsigned int val = index;
103 - if (mux->flags & CLK_MUX_INDEX_ONE)
108 + if (flags & CLK_MUX_INDEX_BIT)
111 + if (flags & CLK_MUX_INDEX_ONE)
117 +EXPORT_SYMBOL_GPL(clk_mux_reindex);
119 +static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
121 + struct clk_mux *mux = to_clk_mux(hw);
123 + unsigned long flags = 0;
125 + index = clk_mux_reindex(index, mux->table, mux->flags);
128 spin_lock_irqsave(mux->lock, flags);
130 @@ -105,7 +123,7 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
133 const struct clk_ops clk_mux_ops = {
134 - .get_parent = clk_mux_get_parent,
135 + .get_parent = _clk_mux_get_parent,
136 .set_parent = clk_mux_set_parent,
137 .determine_rate = __clk_mux_determine_rate,
139 @@ -120,7 +138,7 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name,
140 const char * const *parent_names, u8 num_parents,
142 void __iomem *reg, u8 shift, u32 mask,
143 - u8 clk_mux_flags, u32 *table, spinlock_t *lock)
144 + u8 clk_mux_flags, unsigned int *table, spinlock_t *lock)
148 diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
149 index c56988a..b6b17b5 100644
150 --- a/include/linux/clk-provider.h
151 +++ b/include/linux/clk-provider.h
152 @@ -432,7 +432,7 @@ void clk_unregister_divider(struct clk *clk);
157 + unsigned int *table;
161 @@ -448,6 +448,11 @@ struct clk_mux {
162 extern const struct clk_ops clk_mux_ops;
163 extern const struct clk_ops clk_mux_ro_ops;
165 +unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
166 + unsigned int *table, unsigned long flags);
167 +unsigned int clk_mux_reindex(u8 index, unsigned int *table,
168 + unsigned long flags);
170 struct clk *clk_register_mux(struct device *dev, const char *name,
171 const char * const *parent_names, u8 num_parents,
173 @@ -458,7 +463,7 @@ struct clk *clk_register_mux_table(struct device *dev, const char *name,
174 const char * const *parent_names, u8 num_parents,
176 void __iomem *reg, u8 shift, u32 mask,
177 - u8 clk_mux_flags, u32 *table, spinlock_t *lock);
178 + u8 clk_mux_flags, unsigned int *table, spinlock_t *lock);
180 void clk_unregister_mux(struct clk *clk);