1 From 9263d98e255e1d51b41c752d53e39877728a9419 Mon Sep 17 00:00:00 2001
2 From: Matthew McClintock <mmcclint@codeaurora.org>
3 Date: Tue, 26 Apr 2016 13:14:45 -0500
4 Subject: [PATCH 13/37] spi: qup: call io_config in mode specific function
6 DMA transactions should only only need to call io_config only once, but
7 block mode might call it several times to setup several transactions so
8 it can handle reads/writes larger than the max size per transaction, so
9 we move the call to the do_ functions.
11 This is just refactoring, there should be no functional change
13 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
15 drivers/spi/spi-qup.c | 327 +++++++++++++++++++++++++------------------------
16 1 file changed, 166 insertions(+), 161 deletions(-)
18 --- a/drivers/spi/spi-qup.c
19 +++ b/drivers/spi/spi-qup.c
20 @@ -418,13 +418,170 @@ static void spi_qup_dma_terminate(struct
21 dmaengine_terminate_all(master->dma_rx);
24 -static int spi_qup_do_dma(struct spi_master *master, struct spi_transfer *xfer,
25 +/* prep qup for another spi transaction of specific type */
26 +static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
28 + struct spi_qup *controller = spi_master_get_devdata(spi->master);
29 + u32 config, iomode, control;
30 + unsigned long flags;
32 + reinit_completion(&controller->done);
33 + reinit_completion(&controller->dma_tx_done);
35 + spin_lock_irqsave(&controller->lock, flags);
36 + controller->xfer = xfer;
37 + controller->error = 0;
38 + controller->rx_bytes = 0;
39 + controller->tx_bytes = 0;
40 + spin_unlock_irqrestore(&controller->lock, flags);
42 + if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
43 + dev_err(controller->dev, "cannot set RESET state\n");
47 + switch (controller->mode) {
48 + case QUP_IO_M_MODE_FIFO:
49 + writel_relaxed(controller->n_words,
50 + controller->base + QUP_MX_READ_CNT);
51 + writel_relaxed(controller->n_words,
52 + controller->base + QUP_MX_WRITE_CNT);
53 + /* must be zero for FIFO */
54 + writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
55 + writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
57 + case QUP_IO_M_MODE_BAM:
58 + writel_relaxed(controller->n_words,
59 + controller->base + QUP_MX_INPUT_CNT);
60 + writel_relaxed(controller->n_words,
61 + controller->base + QUP_MX_OUTPUT_CNT);
62 + /* must be zero for BLOCK and BAM */
63 + writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
64 + writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
65 + if (!controller->qup_v1) {
66 + void __iomem *input_cnt;
68 + input_cnt = controller->base + QUP_MX_INPUT_CNT;
70 + * for DMA transfers, both QUP_MX_INPUT_CNT and
71 + * QUP_MX_OUTPUT_CNT must be zero to all cases
72 + * but one. That case is a non-balanced
73 + * transfer when there is only a rx_buf.
76 + writel_relaxed(0, input_cnt);
78 + writel_relaxed(controller->n_words,
81 + writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
84 + case QUP_IO_M_MODE_BLOCK:
85 + writel_relaxed(controller->n_words,
86 + controller->base + QUP_MX_INPUT_CNT);
87 + writel_relaxed(controller->n_words,
88 + controller->base + QUP_MX_OUTPUT_CNT);
89 + /* must be zero for BLOCK and BAM */
90 + writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
91 + writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
94 + dev_err(controller->dev, "unknown mode = %d\n",
99 + iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
100 + /* Set input and output transfer mode */
101 + iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
103 + if (!spi_qup_is_dma_xfer(controller->mode))
104 + iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
106 + iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN;
108 + iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
109 + iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
111 + writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
113 + control = readl_relaxed(controller->base + SPI_IO_CONTROL);
115 + if (spi->mode & SPI_CPOL)
116 + control |= SPI_IO_C_CLK_IDLE_HIGH;
118 + control &= ~SPI_IO_C_CLK_IDLE_HIGH;
120 + writel_relaxed(control, controller->base + SPI_IO_CONTROL);
122 + config = readl_relaxed(controller->base + SPI_CONFIG);
124 + if (spi->mode & SPI_LOOP)
125 + config |= SPI_CONFIG_LOOPBACK;
127 + config &= ~SPI_CONFIG_LOOPBACK;
129 + if (spi->mode & SPI_CPHA)
130 + config &= ~SPI_CONFIG_INPUT_FIRST;
132 + config |= SPI_CONFIG_INPUT_FIRST;
135 + * HS_MODE improves signal stability for spi-clk high rates,
136 + * but is invalid in loop back mode.
138 + if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP))
139 + config |= SPI_CONFIG_HS_MODE;
141 + config &= ~SPI_CONFIG_HS_MODE;
143 + writel_relaxed(config, controller->base + SPI_CONFIG);
145 + config = readl_relaxed(controller->base + QUP_CONFIG);
146 + config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
147 + config |= xfer->bits_per_word - 1;
148 + config |= QUP_CONFIG_SPI_MODE;
150 + if (spi_qup_is_dma_xfer(controller->mode)) {
152 + config |= QUP_CONFIG_NO_OUTPUT;
154 + config |= QUP_CONFIG_NO_INPUT;
157 + writel_relaxed(config, controller->base + QUP_CONFIG);
159 + /* only write to OPERATIONAL_MASK when register is present */
160 + if (!controller->qup_v1) {
164 + * mask INPUT and OUTPUT service flags to prevent IRQs on FIFO
165 + * status change in BAM mode
168 + if (spi_qup_is_dma_xfer(controller->mode))
169 + mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG;
171 + writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
177 +static int spi_qup_do_dma(struct spi_device *spi, struct spi_transfer *xfer,
178 unsigned long timeout)
180 + struct spi_master *master = spi->master;
181 struct spi_qup *qup = spi_master_get_devdata(master);
182 dma_async_tx_callback rx_done = NULL, tx_done = NULL;
185 + ret = spi_qup_io_config(spi, xfer);
189 /* before issuing the descriptors, set the QUP to run */
190 ret = spi_qup_set_state(qup, QUP_STATE_RUN);
192 @@ -467,12 +624,17 @@ unsigned long timeout)
196 -static int spi_qup_do_pio(struct spi_master *master, struct spi_transfer *xfer,
197 +static int spi_qup_do_pio(struct spi_device *spi, struct spi_transfer *xfer,
198 unsigned long timeout)
200 + struct spi_master *master = spi->master;
201 struct spi_qup *qup = spi_master_get_devdata(master);
204 + ret = spi_qup_io_config(spi, xfer);
208 ret = spi_qup_set_state(qup, QUP_STATE_RUN);
210 dev_warn(qup->dev, "cannot set RUN state\n");
211 @@ -619,159 +781,6 @@ static int spi_qup_io_prep(struct spi_de
215 -/* prep qup for another spi transaction of specific type */
216 -static int spi_qup_io_config(struct spi_device *spi, struct spi_transfer *xfer)
218 - struct spi_qup *controller = spi_master_get_devdata(spi->master);
219 - u32 config, iomode, control;
220 - unsigned long flags;
222 - reinit_completion(&controller->done);
223 - reinit_completion(&controller->dma_tx_done);
225 - spin_lock_irqsave(&controller->lock, flags);
226 - controller->xfer = xfer;
227 - controller->error = 0;
228 - controller->rx_bytes = 0;
229 - controller->tx_bytes = 0;
230 - spin_unlock_irqrestore(&controller->lock, flags);
233 - if (spi_qup_set_state(controller, QUP_STATE_RESET)) {
234 - dev_err(controller->dev, "cannot set RESET state\n");
238 - switch (controller->mode) {
239 - case QUP_IO_M_MODE_FIFO:
240 - writel_relaxed(controller->n_words,
241 - controller->base + QUP_MX_READ_CNT);
242 - writel_relaxed(controller->n_words,
243 - controller->base + QUP_MX_WRITE_CNT);
244 - /* must be zero for FIFO */
245 - writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
246 - writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
248 - case QUP_IO_M_MODE_BAM:
249 - writel_relaxed(controller->n_words,
250 - controller->base + QUP_MX_INPUT_CNT);
251 - writel_relaxed(controller->n_words,
252 - controller->base + QUP_MX_OUTPUT_CNT);
253 - /* must be zero for BLOCK and BAM */
254 - writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
255 - writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
256 - if (!controller->qup_v1) {
257 - void __iomem *input_cnt;
259 - input_cnt = controller->base + QUP_MX_INPUT_CNT;
261 - * for DMA transfers, both QUP_MX_INPUT_CNT and
262 - * QUP_MX_OUTPUT_CNT must be zero to all cases
263 - * but one. That case is a non-balanced
264 - * transfer when there is only a rx_buf.
267 - writel_relaxed(0, input_cnt);
269 - writel_relaxed(controller->n_words,
272 - writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
275 - case QUP_IO_M_MODE_BLOCK:
276 - writel_relaxed(controller->n_words,
277 - controller->base + QUP_MX_INPUT_CNT);
278 - writel_relaxed(controller->n_words,
279 - controller->base + QUP_MX_OUTPUT_CNT);
280 - /* must be zero for BLOCK and BAM */
281 - writel_relaxed(0, controller->base + QUP_MX_READ_CNT);
282 - writel_relaxed(0, controller->base + QUP_MX_WRITE_CNT);
285 - dev_err(controller->dev, "unknown mode = %d\n",
290 - iomode = readl_relaxed(controller->base + QUP_IO_M_MODES);
291 - /* Set input and output transfer mode */
292 - iomode &= ~(QUP_IO_M_INPUT_MODE_MASK | QUP_IO_M_OUTPUT_MODE_MASK);
294 - if (!spi_qup_is_dma_xfer(controller->mode))
295 - iomode &= ~(QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN);
297 - iomode |= QUP_IO_M_PACK_EN | QUP_IO_M_UNPACK_EN;
299 - iomode |= (controller->mode << QUP_IO_M_OUTPUT_MODE_MASK_SHIFT);
300 - iomode |= (controller->mode << QUP_IO_M_INPUT_MODE_MASK_SHIFT);
302 - writel_relaxed(iomode, controller->base + QUP_IO_M_MODES);
304 - control = readl_relaxed(controller->base + SPI_IO_CONTROL);
306 - if (spi->mode & SPI_CPOL)
307 - control |= SPI_IO_C_CLK_IDLE_HIGH;
309 - control &= ~SPI_IO_C_CLK_IDLE_HIGH;
311 - writel_relaxed(control, controller->base + SPI_IO_CONTROL);
313 - config = readl_relaxed(controller->base + SPI_CONFIG);
315 - if (spi->mode & SPI_LOOP)
316 - config |= SPI_CONFIG_LOOPBACK;
318 - config &= ~SPI_CONFIG_LOOPBACK;
320 - if (spi->mode & SPI_CPHA)
321 - config &= ~SPI_CONFIG_INPUT_FIRST;
323 - config |= SPI_CONFIG_INPUT_FIRST;
326 - * HS_MODE improves signal stability for spi-clk high rates,
327 - * but is invalid in loop back mode.
329 - if ((xfer->speed_hz >= SPI_HS_MIN_RATE) && !(spi->mode & SPI_LOOP))
330 - config |= SPI_CONFIG_HS_MODE;
332 - config &= ~SPI_CONFIG_HS_MODE;
334 - writel_relaxed(config, controller->base + SPI_CONFIG);
336 - config = readl_relaxed(controller->base + QUP_CONFIG);
337 - config &= ~(QUP_CONFIG_NO_INPUT | QUP_CONFIG_NO_OUTPUT | QUP_CONFIG_N);
338 - config |= xfer->bits_per_word - 1;
339 - config |= QUP_CONFIG_SPI_MODE;
341 - if (spi_qup_is_dma_xfer(controller->mode)) {
343 - config |= QUP_CONFIG_NO_OUTPUT;
345 - config |= QUP_CONFIG_NO_INPUT;
348 - writel_relaxed(config, controller->base + QUP_CONFIG);
350 - /* only write to OPERATIONAL_MASK when register is present */
351 - if (!controller->qup_v1) {
355 - * mask INPUT and OUTPUT service flags to prevent IRQs on FIFO
356 - * status change in BAM mode
359 - if (spi_qup_is_dma_xfer(controller->mode))
360 - mask = QUP_OP_IN_SERVICE_FLAG | QUP_OP_OUT_SERVICE_FLAG;
362 - writel_relaxed(mask, controller->base + QUP_OPERATIONAL_MASK);
368 static int spi_qup_transfer_one(struct spi_master *master,
369 struct spi_device *spi,
370 struct spi_transfer *xfer)
371 @@ -784,18 +793,14 @@ static int spi_qup_transfer_one(struct s
375 - ret = spi_qup_io_config(spi, xfer);
379 timeout = DIV_ROUND_UP(xfer->speed_hz, MSEC_PER_SEC);
380 timeout = DIV_ROUND_UP(xfer->len * 8, timeout);
381 timeout = 100 * msecs_to_jiffies(timeout);
383 if (spi_qup_is_dma_xfer(controller->mode))
384 - ret = spi_qup_do_dma(master, xfer, timeout);
385 + ret = spi_qup_do_dma(spi, xfer, timeout);
387 - ret = spi_qup_do_pio(master, xfer, timeout);
388 + ret = spi_qup_do_pio(spi, xfer, timeout);