1 From 0fba6eceb6e16fa8fd5834d65fcb771fa263a44b Mon Sep 17 00:00:00 2001
2 From: Matthew McClintock <mmcclint@codeaurora.org>
3 Date: Thu, 17 Mar 2016 16:22:28 -0500
4 Subject: [PATCH 24/69] qcom: ipq4019: add USB nodes to ipq4019 SoC device tree
6 This adds the SoC nodes to the ipq4019 device tree
8 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
10 arch/arm/boot/dts/qcom-ipq4019.dtsi | 67 +++++++++++++++++++++++++++++++++++++
11 1 file changed, 67 insertions(+)
13 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
14 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
16 compatible = "qcom,pshold";
20 + usb3_ss_phy: ssphy@9a000 {
21 + compatible = "qca,uni-ssphy";
22 + reg = <0x9a000 0x800>;
23 + reg-names = "phy_base";
24 + resets = <&gcc USB3_UNIPHY_PHY_ARES>;
25 + reset-names = "por_rst";
26 + status = "disabled";
29 + usb3_hs_phy: hsphy@a6000 {
30 + compatible = "qca,baldur-usb3-hsphy";
31 + reg = <0xa6000 0x40>;
32 + reg-names = "phy_base";
33 + resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
34 + reset-names = "por_rst", "srif_rst";
35 + status = "disabled";
39 + compatible = "qcom,dwc3";
40 + #address-cells = <1>;
42 + clocks = <&gcc GCC_USB3_MASTER_CLK>;
43 + clock-names = "core";
45 + status = "disabled";
48 + compatible = "snps,dwc3";
49 + reg = <0x8a00000 0xf8000>;
50 + interrupts = <0 132 0>;
51 + usb-phy = <&usb3_hs_phy>, <&usb3_ss_phy>;
52 + phy-names = "usb2-phy", "usb3-phy";
58 + usb2_hs_phy: hsphy@a8000 {
59 + compatible = "qca,baldur-usb2-hsphy";
60 + reg = <0xa8000 0x40>;
61 + reg-names = "phy_base";
62 + resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
63 + reset-names = "por_rst", "srif_rst";
64 + status = "disabled";
68 + compatible = "qcom,dwc3";
69 + #address-cells = <1>;
71 + clocks = <&gcc GCC_USB2_MASTER_CLK>;
72 + clock-names = "core";
74 + status = "disabled";
77 + compatible = "snps,dwc3";
78 + reg = <0x6000000 0xf8000>;
79 + interrupts = <0 136 0>;
80 + usb-phy = <&usb2_hs_phy>;
81 + phy-names = "usb2-phy";