1 From patchwork Fri Dec 8 09:42:20 2017
2 Content-Type: text/plain; charset="utf-8"
4 Content-Transfer-Encoding: 7bit
5 Subject: [v4,02/12] clk: mux: Split out register accessors for reuse
6 From: Sricharan R <sricharan@codeaurora.org>
7 X-Patchwork-Id: 10102103
8 Message-Id: <1512726150-7204-3-git-send-email-sricharan@codeaurora.org>
9 To: mturquette@baylibre.com, sboyd@codeaurora.org,
10 devicetree@vger.kernel.org, linux-pm@vger.kernel.org,
11 linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
12 viresh.kumar@linaro.org, linux-arm-kernel@lists.infradead.org
13 Cc: sricharan@codeaurora.org
14 Date: Fri, 8 Dec 2017 15:12:20 +0530
16 From: Stephen Boyd <sboyd@codeaurora.org>
18 We want to reuse the logic in clk-mux.c for other clock drivers
19 that don't use readl as register accessors. Fortunately, there
20 really isn't much to the mux code besides the table indirection
21 and quirk flags if you assume any bit shifting and masking has
22 been done already. Pull that logic out into reusable functions
23 that operate on an optional table and some flags so that other
24 drivers can use the same logic.
26 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
28 drivers/clk/clk-mux.c | 75 +++++++++++++++++++++++++++-----------------
29 include/linux/clk-provider.h | 9 ++++--
30 2 files changed, 54 insertions(+), 30 deletions(-)
32 --- a/drivers/clk/clk-mux.c
33 +++ b/drivers/clk/clk-mux.c
35 * parent - parent is adjustable through clk_set_parent
38 -static u8 clk_mux_get_parent(struct clk_hw *hw)
39 +unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
40 + unsigned int *table, unsigned long flags)
42 - struct clk_mux *mux = to_clk_mux(hw);
43 int num_parents = clk_hw_get_num_parents(hw);
47 - * FIXME need a mux-specific flag to determine if val is bitwise or numeric
48 - * e.g. sys_clkin_ck's clksel field is 3 bits wide, but ranges from 0x1
49 - * to 0x7 (index starts at one)
50 - * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
51 - * val = 0x4 really means "bit 2, index starts at bit 0"
53 - val = clk_readl(mux->reg) >> mux->shift;
60 for (i = 0; i < num_parents; i++)
61 - if (mux->table[i] == val)
62 + if (table[i] == val)
67 - if (val && (mux->flags & CLK_MUX_INDEX_BIT))
68 + if (val && (flags & CLK_MUX_INDEX_BIT))
71 - if (val && (mux->flags & CLK_MUX_INDEX_ONE))
72 + if (val && (flags & CLK_MUX_INDEX_ONE))
75 if (val >= num_parents)
76 @@ -62,23 +51,53 @@ static u8 clk_mux_get_parent(struct clk_
80 +EXPORT_SYMBOL_GPL(clk_mux_get_parent);
82 -static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
83 +static u8 _clk_mux_get_parent(struct clk_hw *hw)
85 struct clk_mux *mux = to_clk_mux(hw);
87 - unsigned long flags = 0;
90 - index = mux->table[index];
92 + * FIXME need a mux-specific flag to determine if val is bitwise or
93 + * numeric e.g. sys_clkin_ck's clksel field is 3 bits wide,
94 + * but ranges from 0x1 to 0x7 (index starts at one)
95 + * OTOH, pmd_trace_clk_mux_ck uses a separate bit for each clock, so
96 + * val = 0x4 really means "bit 2, index starts at bit 0"
98 + val = clk_readl(mux->reg) >> mux->shift;
101 + return clk_mux_get_parent(hw, val, mux->table, mux->flags);
104 +unsigned int clk_mux_reindex(u8 index, unsigned int *table,
105 + unsigned long flags)
107 + unsigned int val = index;
112 - if (mux->flags & CLK_MUX_INDEX_BIT)
113 - index = 1 << index;
114 + if (flags & CLK_MUX_INDEX_BIT)
117 - if (mux->flags & CLK_MUX_INDEX_ONE)
119 + if (flags & CLK_MUX_INDEX_ONE)
125 +EXPORT_SYMBOL_GPL(clk_mux_reindex);
127 +static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
129 + struct clk_mux *mux = to_clk_mux(hw);
131 + unsigned long flags = 0;
133 + index = clk_mux_reindex(index, mux->table, mux->flags);
136 spin_lock_irqsave(mux->lock, flags);
138 @@ -102,14 +121,14 @@ static int clk_mux_set_parent(struct clk
141 const struct clk_ops clk_mux_ops = {
142 - .get_parent = clk_mux_get_parent,
143 + .get_parent = _clk_mux_get_parent,
144 .set_parent = clk_mux_set_parent,
145 .determine_rate = __clk_mux_determine_rate,
147 EXPORT_SYMBOL_GPL(clk_mux_ops);
149 const struct clk_ops clk_mux_ro_ops = {
150 - .get_parent = clk_mux_get_parent,
151 + .get_parent = _clk_mux_get_parent,
153 EXPORT_SYMBOL_GPL(clk_mux_ro_ops);
155 @@ -117,7 +136,7 @@ struct clk_hw *clk_hw_register_mux_table
156 const char * const *parent_names, u8 num_parents,
158 void __iomem *reg, u8 shift, u32 mask,
159 - u8 clk_mux_flags, u32 *table, spinlock_t *lock)
160 + u8 clk_mux_flags, unsigned int *table, spinlock_t *lock)
164 --- a/include/linux/clk-provider.h
165 +++ b/include/linux/clk-provider.h
166 @@ -466,7 +466,7 @@ void clk_hw_unregister_divider(struct cl
171 + unsigned int *table;
175 @@ -484,6 +484,11 @@ struct clk_mux {
176 extern const struct clk_ops clk_mux_ops;
177 extern const struct clk_ops clk_mux_ro_ops;
179 +unsigned int clk_mux_get_parent(struct clk_hw *hw, unsigned int val,
180 + unsigned int *table, unsigned long flags);
181 +unsigned int clk_mux_reindex(u8 index, unsigned int *table,
182 + unsigned long flags);
184 struct clk *clk_register_mux(struct device *dev, const char *name,
185 const char * const *parent_names, u8 num_parents,
187 @@ -504,7 +509,7 @@ struct clk_hw *clk_hw_register_mux_table
188 const char * const *parent_names, u8 num_parents,
190 void __iomem *reg, u8 shift, u32 mask,
191 - u8 clk_mux_flags, u32 *table, spinlock_t *lock);
192 + u8 clk_mux_flags, unsigned int *table, spinlock_t *lock);
194 void clk_unregister_mux(struct clk *clk);
195 void clk_hw_unregister_mux(struct clk_hw *hw);