1 From d2ed553484fecdf02fa53bf431599412348afa95 Mon Sep 17 00:00:00 2001
2 From: Matthew McClintock <mmcclint@codeaurora.org>
3 Date: Thu, 17 Mar 2016 16:22:28 -0500
4 Subject: [PATCH 35/37] qcom: ipq4019: add USB nodes to ipq4019 SoC device
7 This adds the SoC nodes to the ipq4019 device tree
9 Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
11 arch/arm/boot/dts/qcom-ipq4019.dtsi | 67 +++++++++++++++++++++++++++++++++++
12 1 file changed, 67 insertions(+)
14 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
15 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
17 compatible = "qcom,pshold";
21 + usb3_ss_phy: ssphy@9a000 {
22 + compatible = "qca,uni-ssphy";
23 + reg = <0x9a000 0x800>;
24 + reg-names = "phy_base";
25 + resets = <&gcc USB3_UNIPHY_PHY_ARES>;
26 + reset-names = "por_rst";
27 + status = "disabled";
30 + usb3_hs_phy: hsphy@a6000 {
31 + compatible = "qca,baldur-usb3-hsphy";
32 + reg = <0xa6000 0x40>;
33 + reg-names = "phy_base";
34 + resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
35 + reset-names = "por_rst", "srif_rst";
36 + status = "disabled";
40 + compatible = "qcom,dwc3";
41 + #address-cells = <1>;
43 + clocks = <&gcc GCC_USB3_MASTER_CLK>;
44 + clock-names = "core";
46 + status = "disabled";
49 + compatible = "snps,dwc3";
50 + reg = <0x8a00000 0xf8000>;
51 + interrupts = <0 132 0>;
52 + usb-phy = <&usb3_hs_phy>, <&usb3_ss_phy>;
53 + phy-names = "usb2-phy", "usb3-phy";
59 + usb2_hs_phy: hsphy@a8000 {
60 + compatible = "qca,baldur-usb2-hsphy";
61 + reg = <0xa8000 0x40>;
62 + reg-names = "phy_base";
63 + resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
64 + reset-names = "por_rst", "srif_rst";
65 + status = "disabled";
69 + compatible = "qcom,dwc3";
70 + #address-cells = <1>;
72 + clocks = <&gcc GCC_USB2_MASTER_CLK>;
73 + clock-names = "core";
75 + status = "disabled";
78 + compatible = "snps,dwc3";
79 + reg = <0x6000000 0xf8000>;
80 + interrupts = <0 136 0>;
81 + usb-phy = <&usb2_hs_phy>;
82 + phy-names = "usb2-phy";