1 From 7fb5976eb0231a06f484a6bde5e5fbfee7ee4f4a Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Fri, 20 Mar 2015 23:45:30 -0700
4 Subject: [PATCH 43/69] clk: qcom: Add Krait clock controller driver
6 The Krait CPU clocks are made up of a primary mux and secondary
7 mux for each CPU and the L2, controlled via cp15 accessors. For
8 Kraits within KPSSv1 each secondary mux accepts a different aux
9 source, but on KPSSv2 each secondary mux accepts the same aux
12 Cc: <devicetree@vger.kernel.org>
13 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
15 .../devicetree/bindings/clock/qcom,krait-cc.txt | 22 ++
16 drivers/clk/qcom/Kconfig | 8 +
17 drivers/clk/qcom/Makefile | 1 +
18 drivers/clk/qcom/krait-cc.c | 352 +++++++++++++++++++++
19 4 files changed, 383 insertions(+)
20 create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
21 create mode 100644 drivers/clk/qcom/krait-cc.c
24 +++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
26 +Krait Clock Controller
32 + Value type: <string>
33 + Definition: must be one of:
40 + Definition: must be 1
44 + kraitcc: clock-controller {
45 + compatible = "qcom,krait-cc-v1";
48 --- a/drivers/clk/qcom/Kconfig
49 +++ b/drivers/clk/qcom/Kconfig
50 @@ -196,6 +196,14 @@ config KPSS_XCC
51 if you want to support CPU frequency scaling on devices such
52 as MSM8960, APQ8064, etc.
55 + tristate "Krait Clock Controller"
56 + depends on COMMON_CLK_QCOM && ARM
59 + Support for the Krait CPU clocks on Qualcomm devices.
60 + Say Y if you want to support CPU frequency scaling.
64 select KRAIT_L2_ACCESSORS
65 --- a/drivers/clk/qcom/Makefile
66 +++ b/drivers/clk/qcom/Makefile
67 @@ -35,3 +35,4 @@ obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
68 obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
69 obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
70 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
71 +obj-$(CONFIG_KRAITCC) += krait-cc.o
73 +++ b/drivers/clk/qcom/krait-cc.c
75 +/* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
77 + * This program is free software; you can redistribute it and/or modify
78 + * it under the terms of the GNU General Public License version 2 and
79 + * only version 2 as published by the Free Software Foundation.
81 + * This program is distributed in the hope that it will be useful,
82 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
83 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
84 + * GNU General Public License for more details.
87 +#include <linux/kernel.h>
88 +#include <linux/init.h>
89 +#include <linux/module.h>
90 +#include <linux/platform_device.h>
91 +#include <linux/err.h>
92 +#include <linux/io.h>
93 +#include <linux/of.h>
94 +#include <linux/of_device.h>
95 +#include <linux/clk.h>
96 +#include <linux/clk-provider.h>
97 +#include <linux/slab.h>
99 +#include "clk-krait.h"
101 +static unsigned int sec_mux_map[] = {
106 +static unsigned int pri_mux_map[] = {
113 +krait_add_div(struct device *dev, int id, const char *s, unsigned offset)
115 + struct krait_div2_clk *div;
116 + struct clk_init_data init = {
118 + .ops = &krait_div2_clk_ops,
119 + .flags = CLK_SET_RATE_PARENT,
121 + const char *p_names[1];
124 + div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
130 + div->lpl = id >= 0;
131 + div->offset = offset;
132 + div->hw.init = &init;
134 + init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
138 + init.parent_names = p_names;
139 + p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
145 + clk = devm_clk_register(dev, &div->hw);
149 + return PTR_ERR_OR_ZERO(clk);
153 +krait_add_sec_mux(struct device *dev, int id, const char *s, unsigned offset,
156 + struct krait_mux_clk *mux;
157 + static const char *sec_mux_list[] = {
161 + struct clk_init_data init = {
162 + .parent_names = sec_mux_list,
163 + .num_parents = ARRAY_SIZE(sec_mux_list),
164 + .ops = &krait_mux_clk_ops,
165 + .flags = CLK_SET_RATE_PARENT,
169 + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
173 + mux->offset = offset;
174 + mux->lpl = id >= 0;
175 + mux->has_safe_parent = true;
179 + mux->parent_map = sec_mux_map;
180 + mux->hw.init = &init;
182 + init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
187 + sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
188 + if (!sec_mux_list[0]) {
189 + clk = ERR_PTR(-ENOMEM);
194 + clk = devm_clk_register(dev, &mux->hw);
197 + kfree(sec_mux_list[0]);
200 + return PTR_ERR_OR_ZERO(clk);
204 +krait_add_pri_mux(struct device *dev, int id, const char *s, unsigned offset)
206 + struct krait_mux_clk *mux;
207 + const char *p_names[3];
208 + struct clk_init_data init = {
209 + .parent_names = p_names,
210 + .num_parents = ARRAY_SIZE(p_names),
211 + .ops = &krait_mux_clk_ops,
212 + .flags = CLK_SET_RATE_PARENT,
216 + mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
218 + return ERR_PTR(-ENOMEM);
220 + mux->has_safe_parent = true;
224 + mux->offset = offset;
225 + mux->lpl = id >= 0;
226 + mux->parent_map = pri_mux_map;
227 + mux->hw.init = &init;
229 + init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
231 + return ERR_PTR(-ENOMEM);
233 + p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
235 + clk = ERR_PTR(-ENOMEM);
239 + p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
241 + clk = ERR_PTR(-ENOMEM);
245 + p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
247 + clk = ERR_PTR(-ENOMEM);
251 + clk = devm_clk_register(dev, &mux->hw);
263 +/* id < 0 for L2, otherwise id == physical CPU number */
264 +static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
273 + offset = 0x4501 + (0x1000 * id);
274 + s = p = kasprintf(GFP_KERNEL, "%d", id);
276 + return ERR_PTR(-ENOMEM);
282 + ret = krait_add_div(dev, id, s, offset);
284 + clk = ERR_PTR(ret);
288 + ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
290 + clk = ERR_PTR(ret);
294 + clk = krait_add_pri_mux(dev, id, s, offset);
300 +static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
302 + unsigned int idx = clkspec->args[0];
303 + struct clk **clks = data;
306 + pr_err("%s: invalid clock index %d\n", __func__, idx);
307 + return ERR_PTR(-EINVAL);
310 + return clks[idx] ? : ERR_PTR(-ENODEV);
313 +static const struct of_device_id krait_cc_match_table[] = {
314 + { .compatible = "qcom,krait-cc-v1", (void *)1UL },
315 + { .compatible = "qcom,krait-cc-v2" },
318 +MODULE_DEVICE_TABLE(of, krait_cc_match_table);
320 +static int krait_cc_probe(struct platform_device *pdev)
322 + struct device *dev = &pdev->dev;
323 + const struct of_device_id *id;
324 + unsigned long cur_rate, aux_rate;
328 + struct clk *l2_pri_mux_clk;
330 + id = of_match_device(krait_cc_match_table, dev);
334 + /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
335 + clk = clk_register_fixed_rate(dev, "qsb", NULL, CLK_IS_ROOT, 1);
337 + return PTR_ERR(clk);
340 + clk = clk_register_fixed_factor(dev, "acpu_aux",
341 + "gpll0_vote", 0, 1, 2);
343 + return PTR_ERR(clk);
346 + /* Krait configurations have at most 4 CPUs and one L2 */
347 + clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
351 + for_each_possible_cpu(cpu) {
352 + clk = krait_add_clks(dev, cpu, id->data);
354 + return PTR_ERR(clk);
358 + l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
359 + if (IS_ERR(l2_pri_mux_clk))
360 + return PTR_ERR(l2_pri_mux_clk);
361 + clks[4] = l2_pri_mux_clk;
364 + * We don't want the CPU or L2 clocks to be turned off at late init
365 + * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
366 + * refcount of these clocks. Any cpufreq/hotplug manager can assume
367 + * that the clocks have already been prepared and enabled by the time
370 + for_each_online_cpu(cpu) {
371 + clk_prepare_enable(l2_pri_mux_clk);
372 + WARN(clk_prepare_enable(clks[cpu]),
373 + "Unable to turn on CPU%d clock", cpu);
377 + * Force reinit of HFPLLs and muxes to overwrite any potential
378 + * incorrect configuration of HFPLLs and muxes by the bootloader.
379 + * While at it, also make sure the cores are running at known rates
380 + * and print the current rate.
382 + * The clocks are set to aux clock rate first to make sure the
383 + * secondary mux is not sourcing off of QSB. The rate is then set to
384 + * two different rates to force a HFPLL reinit under all
387 + cur_rate = clk_get_rate(l2_pri_mux_clk);
388 + aux_rate = 384000000;
389 + if (cur_rate == 1) {
390 + pr_info("L2 @ QSB rate. Forcing new rate.\n");
391 + cur_rate = aux_rate;
393 + clk_set_rate(l2_pri_mux_clk, aux_rate);
394 + clk_set_rate(l2_pri_mux_clk, 2);
395 + clk_set_rate(l2_pri_mux_clk, cur_rate);
396 + pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
397 + for_each_possible_cpu(cpu) {
399 + cur_rate = clk_get_rate(clk);
400 + if (cur_rate == 1) {
401 + pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu);
402 + cur_rate = aux_rate;
404 + clk_set_rate(clk, aux_rate);
405 + clk_set_rate(clk, 2);
406 + clk_set_rate(clk, cur_rate);
407 + pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
410 + of_clk_add_provider(dev->of_node, krait_of_get, clks);
415 +static struct platform_driver krait_cc_driver = {
416 + .probe = krait_cc_probe,
418 + .name = "krait-cc",
419 + .of_match_table = krait_cc_match_table,
422 +module_platform_driver(krait_cc_driver);
424 +MODULE_DESCRIPTION("Krait CPU Clock Driver");
425 +MODULE_LICENSE("GPL v2");
426 +MODULE_ALIAS("platform:krait-cc");