1 From f72c5aa18281c44945fea6181d0d816a7605505c Mon Sep 17 00:00:00 2001
2 From: Georgi Djakov <georgi.djakov@linaro.org>
3 Date: Wed, 18 Mar 2015 17:23:29 +0200
4 Subject: [PATCH 57/69] clk: qcom: Add regmap mux-div clocks support
6 Add support for hardware that can switch both parent clocks and divider
7 at the same time. This avoids generating intermediate frequencies from
8 either the old parent clock and new divider or new parent clock and
9 old divider combinations.
11 Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
13 drivers/clk/qcom/Makefile | 1 +
14 drivers/clk/qcom/clk-regmap-mux-div.c | 272 ++++++++++++++++++++++++++++++++++
15 drivers/clk/qcom/clk-regmap-mux-div.h | 65 ++++++++
16 3 files changed, 338 insertions(+)
17 create mode 100644 drivers/clk/qcom/clk-regmap-mux-div.c
18 create mode 100644 drivers/clk/qcom/clk-regmap-mux-div.h
20 --- a/drivers/clk/qcom/Makefile
21 +++ b/drivers/clk/qcom/Makefile
22 @@ -9,6 +9,7 @@ clk-qcom-y += clk-rcg2.o
23 clk-qcom-y += clk-branch.o
24 clk-qcom-y += clk-regmap-divider.o
25 clk-qcom-y += clk-regmap-mux.o
26 +clk-qcom-y += clk-regmap-mux-div.o
27 clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
28 clk-qcom-y += clk-hfpll.o
31 +++ b/drivers/clk/qcom/clk-regmap-mux-div.c
34 + * Copyright (c) 2015, Linaro Limited
35 + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
37 + * This software is licensed under the terms of the GNU General Public
38 + * License version 2, as published by the Free Software Foundation, and
39 + * may be copied, distributed, and modified under those terms.
41 + * This program is distributed in the hope that it will be useful,
42 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
43 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
44 + * GNU General Public License for more details.
47 +#include <linux/bitops.h>
48 +#include <linux/delay.h>
49 +#include <linux/export.h>
50 +#include <linux/kernel.h>
51 +#include <linux/regmap.h>
53 +#include "clk-regmap-mux-div.h"
56 +#define CMD_RCGR_UPDATE BIT(0)
57 +#define CMD_RCGR_DIRTY_CFG BIT(4)
58 +#define CMD_RCGR_ROOT_OFF BIT(31)
61 +#define to_clk_regmap_mux_div(_hw) \
62 + container_of(to_clk_regmap(_hw), struct clk_regmap_mux_div, clkr)
64 +int __mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div)
68 + const char *name = clk_hw_get_name(&md->clkr.hw);
70 + val = (div << md->hid_shift) | (src << md->src_shift);
71 + mask = ((BIT(md->hid_width) - 1) << md->hid_shift) |
72 + ((BIT(md->src_width) - 1) << md->src_shift);
74 + ret = regmap_update_bits(md->clkr.regmap, CFG_RCGR + md->reg_offset,
79 + ret = regmap_update_bits(md->clkr.regmap, CMD_RCGR + md->reg_offset,
80 + CMD_RCGR_UPDATE, CMD_RCGR_UPDATE);
84 + /* Wait for update to take effect */
85 + for (count = 500; count > 0; count--) {
86 + ret = regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset,
90 + if (!(val & CMD_RCGR_UPDATE))
95 + pr_err("%s: RCG did not update its configuration", name);
99 +static void __mux_div_get_src_div(struct clk_regmap_mux_div *md, u32 *src,
102 + u32 val, __div, __src;
103 + const char *name = clk_hw_get_name(&md->clkr.hw);
105 + regmap_read(md->clkr.regmap, CMD_RCGR + md->reg_offset, &val);
107 + if (val & CMD_RCGR_DIRTY_CFG) {
108 + pr_err("%s: RCG configuration is pending\n", name);
112 + regmap_read(md->clkr.regmap, CFG_RCGR + md->reg_offset, &val);
113 + __src = (val >> md->src_shift);
114 + __src &= BIT(md->src_width) - 1;
117 + __div = (val >> md->hid_shift);
118 + __div &= BIT(md->hid_width) - 1;
122 +static int mux_div_enable(struct clk_hw *hw)
124 + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
126 + return __mux_div_set_src_div(md, md->src, md->div);
129 +static inline bool is_better_rate(unsigned long req, unsigned long best,
132 + return (req <= new && new < best) || (best < req && best < new);
135 +static int mux_div_determine_rate(struct clk_hw *hw,
136 + struct clk_rate_request *req)
138 + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
139 + unsigned int i, div, max_div;
140 + unsigned long actual_rate, best_rate = 0;
141 + unsigned long req_rate = req->rate;
143 + for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
144 + struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
145 + unsigned long parent_rate = clk_hw_get_rate(parent);
147 + max_div = BIT(md->hid_width) - 1;
148 + for (div = 1; div < max_div; div++) {
149 + parent_rate = mult_frac(req_rate, div, 2);
150 + parent_rate = clk_hw_round_rate(parent, parent_rate);
151 + actual_rate = mult_frac(parent_rate, 2, div);
153 + if (is_better_rate(req_rate, best_rate, actual_rate)) {
154 + best_rate = actual_rate;
155 + req->rate = best_rate;
156 + req->best_parent_rate = parent_rate;
157 + req->best_parent_hw = parent;
160 + if (actual_rate < req_rate || best_rate <= req_rate)
171 +static int __mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
172 + unsigned long prate, u32 src)
174 + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
176 + u32 div, max_div, best_src = 0, best_div = 0;
178 + unsigned long actual_rate, best_rate = 0;
180 + for (i = 0; i < clk_hw_get_num_parents(hw); i++) {
181 + struct clk_hw *parent = clk_hw_get_parent_by_index(hw, i);
182 + unsigned long parent_rate = clk_hw_get_rate(parent);
184 + max_div = BIT(md->hid_width) - 1;
185 + for (div = 1; div < max_div; div++) {
186 + parent_rate = mult_frac(rate, div, 2);
187 + parent_rate = clk_hw_round_rate(parent, parent_rate);
188 + actual_rate = mult_frac(parent_rate, 2, div);
190 + if (is_better_rate(rate, best_rate, actual_rate)) {
191 + best_rate = actual_rate;
192 + best_src = md->parent_map[i].cfg;
193 + best_div = div - 1;
196 + if (actual_rate < rate || best_rate <= rate)
201 + ret = __mux_div_set_src_div(md, best_src, best_div);
203 + md->div = best_div;
204 + md->src = best_src;
210 +static u8 mux_div_get_parent(struct clk_hw *hw)
212 + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
213 + const char *name = clk_hw_get_name(hw);
214 + u32 i, div, src = 0;
216 + __mux_div_get_src_div(md, &src, &div);
218 + for (i = 0; i < clk_hw_get_num_parents(hw); i++)
219 + if (src == md->parent_map[i].cfg)
222 + pr_err("%s: Can't find parent with src %d\n", name, src);
226 +static int mux_div_set_parent(struct clk_hw *hw, u8 index)
228 + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
230 + return __mux_div_set_src_div(md, md->parent_map[index].cfg, md->div);
233 +static int mux_div_set_rate(struct clk_hw *hw,
234 + unsigned long rate, unsigned long prate)
236 + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
238 + return __mux_div_set_rate_and_parent(hw, rate, prate, md->src);
241 +static int mux_div_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
242 + unsigned long prate, u8 index)
244 + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
246 + return __mux_div_set_rate_and_parent(hw, rate, prate,
247 + md->parent_map[index].cfg);
250 +static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate)
252 + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
254 + int i, num_parents = clk_hw_get_num_parents(hw);
255 + const char *name = clk_hw_get_name(hw);
257 + __mux_div_get_src_div(md, &src, &div);
258 + for (i = 0; i < num_parents; i++)
259 + if (src == md->parent_map[i].cfg) {
260 + struct clk_hw *p = clk_hw_get_parent_by_index(hw, i);
261 + unsigned long parent_rate = clk_hw_get_rate(p);
263 + return mult_frac(parent_rate, 2, div + 1);
266 + pr_err("%s: Can't find parent %d\n", name, src);
270 +static struct clk_hw *mux_div_get_safe_parent(struct clk_hw *hw,
271 + unsigned long *safe_freq)
274 + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
277 + *safe_freq = md->safe_freq;
279 + for (i = 0; i < clk_hw_get_num_parents(hw); i++)
280 + if (md->safe_src == md->parent_map[i].cfg)
283 + return clk_hw_get_parent_by_index(hw, i);
286 +static void mux_div_disable(struct clk_hw *hw)
288 + struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
290 + __mux_div_set_src_div(md, md->safe_src, md->safe_div);
293 +const struct clk_ops clk_regmap_mux_div_ops = {
294 + .enable = mux_div_enable,
295 + .disable = mux_div_disable,
296 + .get_parent = mux_div_get_parent,
297 + .set_parent = mux_div_set_parent,
298 + .set_rate = mux_div_set_rate,
299 + .set_rate_and_parent = mux_div_set_rate_and_parent,
300 + .determine_rate = mux_div_determine_rate,
301 + .recalc_rate = mux_div_recalc_rate,
302 + .get_safe_parent = mux_div_get_safe_parent,
304 +EXPORT_SYMBOL_GPL(clk_regmap_mux_div_ops);
306 +++ b/drivers/clk/qcom/clk-regmap-mux-div.h
309 + * Copyright (c) 2015, Linaro Limited
310 + * Copyright (c) 2014, The Linux Foundation. All rights reserved.
312 + * This software is licensed under the terms of the GNU General Public
313 + * License version 2, as published by the Free Software Foundation, and
314 + * may be copied, distributed, and modified under those terms.
316 + * This program is distributed in the hope that it will be useful,
317 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
318 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
319 + * GNU General Public License for more details.
322 +#ifndef __QCOM_CLK_REGMAP_MUX_DIV_H__
323 +#define __QCOM_CLK_REGMAP_MUX_DIV_H__
325 +#include <linux/clk-provider.h>
326 +#include "clk-rcg.h"
327 +#include "clk-regmap.h"
330 + * struct mux_div_clk - combined mux/divider clock
331 + * @reg_offset: offset of the mux/divider register
332 + * @hid_width: number of bits in half integer divider
333 + * @hid_shift: lowest bit of hid value field
334 + * @src_width: number of bits in source select
335 + * @src_shift: lowest bit of source select field
336 + * @div: the divider raw configuration value
337 + * @src: the mux index which will be used if the clock is enabled
338 + * @safe_src: the safe source mux value we switch to, while the main PLL is
340 + * @safe_div: the safe divider value that we set, while the main PLL is
342 + * @safe_freq: When switching rates from A to B, the mux div clock will
343 + * instead switch from A -> safe_freq -> B. This allows the
344 + * mux_div clock to change rates while enabled, even if this
345 + * behavior is not supported by the parent clocks.
346 + * If changing the rate of parent A also causes the rate of
347 + * parent B to change, then safe_freq must be defined.
348 + * safe_freq is expected to have a source clock which is always
349 + * on and runs at only one rate.
350 + * @parent_map: pointer to parent_map struct
351 + * @clkr: handle between common and hardware-specific interfaces
354 +struct clk_regmap_mux_div {
364 + unsigned long safe_freq;
365 + const struct parent_map *parent_map;
366 + struct clk_regmap clkr;
369 +extern const struct clk_ops clk_regmap_mux_div_ops;
370 +int __mux_div_set_src_div(struct clk_regmap_mux_div *md, u32 src, u32 div);