1 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
2 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
9 compatible = "qcom,krait";
10 enable-method = "qcom,kpss-acc-v1";
13 next-level-cache = <&L2>;
20 compatible = "qcom,krait";
21 enable-method = "qcom,kpss-acc-v1";
24 next-level-cache = <&L2>;
30 + smem: smem@41000000 {
31 reg = <0x41000000 0x200000>;
35 gpio-ranges = <&qcom_pinmux 0 0 69>;
38 + #address-cells = <0>;
39 #interrupt-cells = <2>;
40 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
43 function = "pcie3_rst";
44 drive-strength = <12>;
51 intc: interrupt-controller@2000000 {
52 compatible = "qcom,msm-qgic2";
54 + #address-cells = <0>;
55 #interrupt-cells = <3>;
56 reg = <0x02000000 0x1000>,
59 acc0: clock-controller@2088000 {
60 compatible = "qcom,kpss-acc-v1";
61 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
62 + clock-output-names = "acpu0_aux";
65 acc1: clock-controller@2098000 {
66 compatible = "qcom,kpss-acc-v1";
67 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
68 + clock-output-names = "acpu1_aux";
71 saw0: regulator@2089000 {
72 - compatible = "qcom,saw2";
73 + compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
74 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
78 saw1: regulator@2099000 {
79 - compatible = "qcom,saw2";
80 + compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
81 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
86 syscon-tcsr = <&tcsr>;
89 + gsbi2_serial: serial@12490000 {
90 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
91 reg = <0x12490000 0x1000>,
95 syscon-tcsr = <&tcsr>;
98 + gsbi5_serial: serial@1a240000 {
99 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
100 reg = <0x1a240000 0x1000>,
107 + sata: sata@29000000 {
108 compatible = "qcom,ipq806x-ahci", "generic-ahci";
109 reg = <0x29000000 0x180>;
111 @@ -430,6 +430,16 @@ qfprom: qfprom@700000 {
112 reg = <0x00700000 0x1000>;
113 #address-cells = <1>;
116 + tsens_calib: calib@400 {
119 + tsens_backup: backup@410 {
122 + speedbin_efuse: speedbin@0c0 {
127 gcc: clock-controller@900000 {
128 @@ -437,9 +447,21 @@ gcc: clock-controller@900000 {
130 gcc: clock-controller@900000 {
131 - compatible = "qcom,gcc-ipq8064";
132 + compatible = "qcom,gcc-ipq8064", "syscon";
133 reg = <0x00900000 0x4000>;
136 + #power-domain-cells = <1>;
138 + tsens: thermal-sensor@900000 {
139 + compatible = "qcom,ipq8064-tsens";
141 + nvmem-cells = <&tsens_calib>, <&tsens_backup>;
142 + nvmem-cell-names = "calib", "calib_backup";
143 + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
144 + interrupt-names = "uplow";
145 + #thermal-sensor-cells = <1>;
146 + #qcom,sensors = <11>;
150 tcsr: syscon@1a400000 {
151 @@ -625,13 +629,13 @@
156 - compatible = "simple-bus";
158 + compatible = "arm,amba-bus";
159 #address-cells = <1>;
164 + sdcc1: sdcc@12400000 {
166 compatible = "arm,pl18x", "arm,primecell";
167 arm,primecell-periphid = <0x00051180>;
168 @@ -645,13 +649,12 @@
173 vmmc-supply = <&vsdcc_fixed>;
174 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
175 dma-names = "tx", "rx";
179 + sdcc3: sdcc@12180000 {
180 compatible = "arm,pl18x", "arm,primecell";
181 arm,primecell-periphid = <0x00051180>;