1 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
2 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
4 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/soc/qcom,gsbi.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 +#include <dt-bindings/mfd/qcom-rpm.h>
8 +#include <dt-bindings/clock/qcom,rpmcc.h>
13 next-level-cache = <&L2>;
16 + clocks = <&kraitcc 0>, <&kraitcc 4>;
17 + clock-names = "cpu", "l2";
18 + clock-latency = <100000>;
19 + cpu-supply = <&smb208_s2a>;
20 + operating-points-v2 = <&opp_table0>;
21 + voltage-tolerance = <5>;
22 + cooling-min-state = <0>;
23 + cooling-max-state = <10>;
24 + #cooling-cells = <2>;
25 + cpu-idle-states = <&CPU_SPC>;
30 next-level-cache = <&L2>;
33 + clocks = <&kraitcc 1>, <&kraitcc 4>;
34 + clock-names = "cpu", "l2";
35 + clock-latency = <100000>;
36 + cpu-supply = <&smb208_s2b>;
37 + operating-points-v2 = <&opp_table0>;
38 + voltage-tolerance = <5>;
39 + cooling-min-state = <0>;
40 + cooling-max-state = <10>;
41 + #cooling-cells = <2>;
42 + cpu-idle-states = <&CPU_SPC>;
47 + compatible = "qcom,idle-state-spc";
48 + status = "disabled";
49 + entry-latency-us = <400>;
50 + exit-latency-us = <900>;
51 + min-residency-us = <3000>;
57 - compatible = "cache";
59 + opp_table_l2: opp_table_l2 {
60 + compatible = "operating-points-v2";
63 + opp-hz = /bits/ 64 <384000000>;
64 + opp-microvolt = <1100000>;
65 + clock-latency-ns = <100000>;
70 + opp-hz = /bits/ 64 <1000000000>;
71 + opp-microvolt = <1100000>;
72 + clock-latency-ns = <100000>;
77 + opp-hz = /bits/ 64 <1200000000>;
78 + opp-microvolt = <1150000>;
79 + clock-latency-ns = <100000>;
84 + opp_table0: opp_table0 {
85 + compatible = "operating-points-v2-kryo-cpu";
86 + nvmem-cells = <&speedbin_efuse>;
89 + opp-hz = /bits/ 64 <384000000>;
90 + opp-microvolt-speed0-pvs0-v0 = <950000 1000000 1050000>;
91 + opp-microvolt-speed0-pvs1-v0 = <878750 925000 971250>;
92 + opp-microvolt-speed0-pvs2-v0 = <831250 875000 918750>;
93 + opp-microvolt-speed0-pvs3-v0 = <760000 800000 840000>;
94 + opp-supported-hw = <0x1>;
95 + clock-latency-ns = <100000>;
100 + opp-hz = /bits/ 64 <600000000>;
101 + opp-microvolt-speed0-pvs0-v0 = <997500 1050000 1102500>;
102 + opp-microvolt-speed0-pvs1-v0 = <926250 975000 1023750>;
103 + opp-microvolt-speed0-pvs2-v0 = <878750 925000 971250>;
104 + opp-microvolt-speed0-pvs3-v0 = <807500 850000 892500>;
105 + opp-supported-hw = <0x1>;
106 + clock-latency-ns = <100000>;
111 + opp-hz = /bits/ 64 <800000000>;
112 + opp-microvolt-speed0-pvs0-v0 = <1045000 1100000 1155000>;
113 + opp-microvolt-speed0-pvs1-v0 = <973750 1025000 1076250>;
114 + opp-microvolt-speed0-pvs2-v0 = <945250 995000 1044750>;
115 + opp-microvolt-speed0-pvs3-v0 = <855000 900000 945000>;
116 + opp-supported-hw = <0x1>;
117 + clock-latency-ns = <100000>;
122 + opp-hz = /bits/ 64 <1000000000>;
123 + opp-microvolt-speed0-pvs0-v0 = <1092500 1150000 1207500>;
124 + opp-microvolt-speed0-pvs1-v0 = <1021250 1075000 1128750>;
125 + opp-microvolt-speed0-pvs2-v0 = <973750 1025000 1076250>;
126 + opp-microvolt-speed0-pvs3-v0 = <902500 950000 997500>;
127 + opp-supported-hw = <0x1>;
128 + clock-latency-ns = <100000>;
133 + opp-hz = /bits/ 64 <1200000000>;
134 + opp-microvolt-speed0-pvs0-v0 = <1140000 1200000 1260000>;
135 + opp-microvolt-speed0-pvs1-v0 = <1068750 1125000 1181250>;
136 + opp-microvolt-speed0-pvs2-v0 = <1021250 1075000 1128750>;
137 + opp-microvolt-speed0-pvs3-v0 = <950000 1000000 1050000>;
138 + opp-supported-hw = <0x1>;
139 + clock-latency-ns = <100000>;
144 + opp-hz = /bits/ 64 <1400000000>;
145 + opp-microvolt-speed0-pvs0-v0 = <1187500 1250000 1312500>;
146 + opp-microvolt-speed0-pvs1-v0 = <1116250 1175000 1233750>;
147 + opp-microvolt-speed0-pvs2-v0 = <1068750 1125000 1181250>;
148 + opp-microvolt-speed0-pvs3-v0 = <997500 1050000 1102500>;
149 + opp-supported-hw = <0x1>;
150 + clock-latency-ns = <100000>;
157 + polling-delay-passive = <0>;
158 + polling-delay = <0>;
159 + thermal-sensors = <&tsens 0>;
163 + temperature = <105000>;
164 + hysteresis = <2000>;
169 + temperature = <95000>;
170 + hysteresis = <2000>;
177 + polling-delay-passive = <0>;
178 + polling-delay = <0>;
179 + thermal-sensors = <&tsens 1>;
183 + temperature = <105000>;
184 + hysteresis = <2000>;
189 + temperature = <95000>;
190 + hysteresis = <2000>;
197 + polling-delay-passive = <0>;
198 + polling-delay = <0>;
199 + thermal-sensors = <&tsens 2>;
203 + temperature = <105000>;
204 + hysteresis = <2000>;
209 + temperature = <95000>;
210 + hysteresis = <2000>;
217 + polling-delay-passive = <0>;
218 + polling-delay = <0>;
219 + thermal-sensors = <&tsens 3>;
223 + temperature = <105000>;
224 + hysteresis = <2000>;
229 + temperature = <95000>;
230 + hysteresis = <2000>;
237 + polling-delay-passive = <0>;
238 + polling-delay = <0>;
239 + thermal-sensors = <&tsens 4>;
243 + temperature = <105000>;
244 + hysteresis = <2000>;
249 + temperature = <95000>;
250 + hysteresis = <2000>;
257 + polling-delay-passive = <0>;
258 + polling-delay = <0>;
259 + thermal-sensors = <&tsens 5>;
263 + temperature = <105000>;
264 + hysteresis = <2000>;
269 + temperature = <95000>;
270 + hysteresis = <2000>;
277 + polling-delay-passive = <0>;
278 + polling-delay = <0>;
279 + thermal-sensors = <&tsens 6>;
283 + temperature = <105000>;
284 + hysteresis = <2000>;
289 + temperature = <95000>;
290 + hysteresis = <2000>;
297 + polling-delay-passive = <0>;
298 + polling-delay = <0>;
299 + thermal-sensors = <&tsens 7>;
303 + temperature = <105000>;
304 + hysteresis = <2000>;
309 + temperature = <95000>;
310 + hysteresis = <2000>;
317 + polling-delay-passive = <0>;
318 + polling-delay = <0>;
319 + thermal-sensors = <&tsens 8>;
323 + temperature = <105000>;
324 + hysteresis = <2000>;
329 + temperature = <95000>;
330 + hysteresis = <2000>;
337 + polling-delay-passive = <0>;
338 + polling-delay = <0>;
339 + thermal-sensors = <&tsens 9>;
343 + temperature = <105000>;
344 + hysteresis = <2000>;
349 + temperature = <95000>;
350 + hysteresis = <2000>;
356 + tsens_tz_sensor10 {
357 + polling-delay-passive = <0>;
358 + polling-delay = <0>;
359 + thermal-sensors = <&tsens 10>;
363 + temperature = <105000>;
364 + hysteresis = <2000>;
369 + temperature = <95000>;
370 + hysteresis = <2000>;
378 device_type = "memory";
385 + compatible = "qcom,fab-scaling";
386 + clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
387 + clock-names = "apps-fab-clk", "ddr-fab-clk";
388 + fab_freq_high = <533000000>;
389 + fab_freq_nominal = <400000000>;
390 + cpu_freq_threshold = <1000000000>;
395 compatible = "qcom,scm-ipq806x", "qcom,scm";
397 reg-names = "lpass-lpaif";
401 + compatible = "qcom,krait-cache", "cache";
403 + qcom,saw = <&saw_l2>;
405 + clocks = <&kraitcc 4>;
406 + clock-names = "l2";
407 + l2-supply = <&smb208_s1a>;
408 + operating-points-v2 = <&opp_table_l2>;
412 + compatible = "qcom,rpm-ipq8064";
413 + reg = <0x108000 0x1000>;
414 + qcom,ipc = <&l2cc 0x8 2>;
416 + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
417 + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
418 + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
419 + interrupt-names = "ack", "err", "wakeup";
421 + clocks = <&gcc RPM_MSG_RAM_H_CLK>;
422 + clock-names = "ram";
424 + #address-cells = <1>;
427 + rpmcc: clock-controller {
428 + compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
429 + #clock-cells = <1>;
433 + compatible = "qcom,rpm-smb208-regulators";
436 + regulator-min-microvolt = <1050000>;
437 + regulator-max-microvolt = <1150000>;
439 + qcom,switch-mode-frequency = <1200000>;
443 + regulator-min-microvolt = <1050000>;
444 + regulator-max-microvolt = <1150000>;
446 + qcom,switch-mode-frequency = <1200000>;
450 + regulator-min-microvolt = < 800000>;
451 + regulator-max-microvolt = <1250000>;
453 + qcom,switch-mode-frequency = <1200000>;
457 + regulator-min-microvolt = < 800000>;
458 + regulator-max-microvolt = <1250000>;
460 + qcom,switch-mode-frequency = <1200000>;
466 + compatible = "qcom,prng";
467 + reg = <0x1a500000 0x200>;
468 + clocks = <&gcc PRNG_CLK>;
469 + clock-names = "core";
472 qcom_pinmux: pinmux@800000 {
473 compatible = "qcom,ipq8064-pinctrl";
474 reg = <0x800000 0x4000>;
479 + i2c4_pins: i2c4_pinmux {
481 + pins = "gpio12", "gpio13";
482 + function = "gsbi4";
483 + drive-strength = <12>;
490 pins = "gpio18", "gpio19", "gpio21";
495 + nand_pins: nand_pins {
497 + pins = "gpio34", "gpio35", "gpio36",
498 + "gpio37", "gpio38";
500 + drive-strength = <10>;
507 + drive-strength = <10>;
512 + pins = "gpio40", "gpio41", "gpio42",
513 + "gpio43", "gpio44", "gpio45",
514 + "gpio46", "gpio47";
516 + drive-strength = <10>;
521 + mdio0_pins: mdio0_pins {
523 + pins = "gpio0", "gpio1";
525 + drive-strength = <8>;
530 + rgmii2_pins: rgmii2_pins {
532 + pins = "gpio27", "gpio28", "gpio29",
533 + "gpio30", "gpio31", "gpio32",
534 + "gpio51", "gpio52", "gpio59",
535 + "gpio60", "gpio61", "gpio62";
536 + function = "rgmii2";
537 + drive-strength = <8>;
542 leds_pins: leds_pins {
544 pins = "gpio7", "gpio8", "gpio9",
546 clock-output-names = "acpu1_aux";
549 + l2cc: clock-controller@2011000 {
550 + compatible = "qcom,kpss-gcc", "syscon";
551 + reg = <0x2011000 0x1000>;
552 + clock-output-names = "acpu_l2_aux";
555 + kraitcc: clock-controller {
556 + compatible = "qcom,krait-cc-v1";
557 + #clock-cells = <1>;
560 saw0: regulator@2089000 {
561 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
562 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
567 + saw_l2: regulator@02012000 {
568 + compatible = "qcom,saw2", "syscon";
569 + reg = <0x02012000 0x1000>;
573 + sic_non_secure: sic-non-secure@12100000 {
574 + compatible = "syscon";
575 + reg = <0x12100000 0x10000>;
578 gsbi2: gsbi@12480000 {
579 compatible = "qcom,gsbi-v1.0.0";
585 + sfpb_mutex_block: syscon@1200600 {
586 + compatible = "syscon";
587 + reg = <0x01200600 0x100>;
590 + hs_phy_0: hs_phy_0 {
591 + compatible = "qcom,ipq806x-usb-phy-hs";
592 + reg = <0x110f8800 0x30>;
593 + clocks = <&gcc USB30_0_UTMI_CLK>;
594 + clock-names = "ref";
598 + ss_phy_0: ss_phy_0 {
599 + compatible = "qcom,ipq806x-usb-phy-ss";
600 + reg = <0x110f8830 0x30>;
601 + clocks = <&gcc USB30_0_MASTER_CLK>;
602 + clock-names = "ref";
606 + usb3_0: usb3@110f8800 {
607 + compatible = "qcom,dwc3", "syscon";
608 + #address-cells = <1>;
610 + reg = <0x110f8800 0x8000>;
611 + clocks = <&gcc USB30_0_MASTER_CLK>;
612 + clock-names = "core";
616 + resets = <&gcc USB30_0_MASTER_RESET>;
617 + reset-names = "master";
619 + status = "disabled";
621 + dwc3_0: dwc3@11000000 {
622 + compatible = "snps,dwc3";
623 + reg = <0x11000000 0xcd00>;
624 + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
625 + phys = <&hs_phy_0>, <&ss_phy_0>;
626 + phy-names = "usb2-phy", "usb3-phy";
628 + snps,dis_u3_susphy_quirk;
632 + hs_phy_1: hs_phy_1 {
633 + compatible = "qcom,ipq806x-usb-phy-hs";
634 + reg = <0x100f8800 0x30>;
635 + clocks = <&gcc USB30_1_UTMI_CLK>;
636 + clock-names = "ref";
640 + ss_phy_1: ss_phy_1 {
641 + compatible = "qcom,ipq806x-usb-phy-ss";
642 + reg = <0x100f8830 0x30>;
643 + clocks = <&gcc USB30_1_MASTER_CLK>;
644 + clock-names = "ref";
648 + usb3_1: usb3@100f8800 {
649 + compatible = "qcom,dwc3", "syscon";
650 + #address-cells = <1>;
652 + reg = <0x100f8800 0x8000>;
653 + clocks = <&gcc USB30_1_MASTER_CLK>;
654 + clock-names = "core";
658 + resets = <&gcc USB30_1_MASTER_RESET>;
659 + reset-names = "master";
661 + status = "disabled";
663 + dwc3_1: dwc3@10000000 {
664 + compatible = "snps,dwc3";
665 + reg = <0x10000000 0xcd00>;
666 + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
667 + phys = <&hs_phy_1>, <&ss_phy_1>;
668 + phy-names = "usb2-phy", "usb3-phy";
670 + snps,dis_u3_susphy_quirk;
674 pcie0: pci@1b500000 {
675 compatible = "qcom,pcie-ipq8064";
676 reg = <0x1b500000 0x1000
677 @@ -739,6 +1332,59 @@
681 + adm_dma: dma@18300000 {
682 + compatible = "qcom,adm";
683 + reg = <0x18300000 0x100000>;
684 + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
687 + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
688 + clock-names = "core", "iface";
690 + resets = <&gcc ADM0_RESET>,
691 + <&gcc ADM0_PBUS_RESET>,
692 + <&gcc ADM0_C0_RESET>,
693 + <&gcc ADM0_C1_RESET>,
694 + <&gcc ADM0_C2_RESET>;
695 + reset-names = "clk", "pbus", "c0", "c1", "c2";
698 + status = "disabled";
701 + nand_controller: nand-controller@1ac00000 {
702 + compatible = "qcom,ipq806x-nand";
703 + reg = <0x1ac00000 0x800>;
705 + clocks = <&gcc EBI2_CLK>,
706 + <&gcc EBI2_AON_CLK>;
707 + clock-names = "core", "aon";
709 + dmas = <&adm_dma 3>;
710 + dma-names = "rxtx";
711 + qcom,cmd-crci = <15>;
712 + qcom,data-crci = <3>;
714 + status = "disabled";
716 + #address-cells = <1>;
720 + mdio0: mdio@37000000 {
721 + #address-cells = <1>;
724 + compatible = "qcom,ipq8064-mdio", "syscon";
725 + reg = <0x37000000 0x200000>;
726 + resets = <&gcc GMAC_CORE1_RESET>;
727 + reset-names = "stmmaceth";
728 + clocks = <&gcc GMAC_CORE1_CLK>;
729 + clock-names = "stmmaceth";
731 + status = "disabled";
734 vsdcc_fixed: vsdcc-regulator {
735 compatible = "regulator-fixed";
736 regulator-name = "SDCC Power";
737 @@ -814,4 +1460,17 @@
742 + sfpb_mutex: sfpb-mutex {
743 + compatible = "qcom,sfpb-mutex";
744 + syscon = <&sfpb_mutex_block 4 4>;
746 + #hwlock-cells = <1>;
750 + compatible = "qcom,smem";
751 + memory-region = <&smem>;
752 + hwlocks = <&sfpb_mutex 3>;