1 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
2 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
4 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/soc/qcom,gsbi.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 +#include <dt-bindings/mfd/qcom-rpm.h>
8 +#include <dt-bindings/clock/qcom,rpmcc.h>
13 next-level-cache = <&L2>;
16 + clocks = <&kraitcc 0>, <&kraitcc 4>;
17 + clock-names = "cpu", "l2";
18 + clock-latency = <100000>;
19 + cpu-supply = <&smb208_s2a>;
20 + operating-points-v2 = <&opp_table0>;
21 + voltage-tolerance = <5>;
22 + cooling-min-state = <0>;
23 + cooling-max-state = <10>;
24 + #cooling-cells = <2>;
25 + cpu-idle-states = <&CPU_SPC>;
30 next-level-cache = <&L2>;
33 + clocks = <&kraitcc 1>, <&kraitcc 4>;
34 + clock-names = "cpu", "l2";
35 + clock-latency = <100000>;
36 + cpu-supply = <&smb208_s2b>;
37 + operating-points-v2 = <&opp_table0>;
38 + voltage-tolerance = <5>;
39 + cooling-min-state = <0>;
40 + cooling-max-state = <10>;
41 + #cooling-cells = <2>;
42 + cpu-idle-states = <&CPU_SPC>;
47 + compatible = "qcom,idle-state-spc";
48 + status = "disabled";
49 + entry-latency-us = <400>;
50 + exit-latency-us = <900>;
51 + min-residency-us = <3000>;
57 - compatible = "cache";
59 + opp_table_l2: opp_table_l2 {
60 + compatible = "operating-points-v2";
63 + opp-hz = /bits/ 64 <384000000>;
64 + opp-microvolt = <1100000>;
65 + clock-latency-ns = <100000>;
70 + opp-hz = /bits/ 64 <1000000000>;
71 + opp-microvolt = <1100000>;
72 + clock-latency-ns = <100000>;
77 + opp-hz = /bits/ 64 <1200000000>;
78 + opp-microvolt = <1150000>;
79 + clock-latency-ns = <100000>;
84 + opp_table0: opp_table0 {
85 + compatible = "operating-points-v2-kryo-cpu";
86 + nvmem-cells = <&speedbin_efuse>;
89 + * Voltage thresholds are <target min max>
92 + opp-hz = /bits/ 64 <384000000>;
93 + opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>;
94 + opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>;
95 + opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>;
96 + opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>;
97 + opp-supported-hw = <0x1>;
98 + clock-latency-ns = <100000>;
103 + opp-hz = /bits/ 64 <600000000>;
104 + opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>;
105 + opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>;
106 + opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>;
107 + opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>;
108 + opp-supported-hw = <0x1>;
109 + clock-latency-ns = <100000>;
114 + opp-hz = /bits/ 64 <800000000>;
115 + opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>;
116 + opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>;
117 + opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>;
118 + opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>;
119 + opp-supported-hw = <0x1>;
120 + clock-latency-ns = <100000>;
125 + opp-hz = /bits/ 64 <1000000000>;
126 + opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>;
127 + opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>;
128 + opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>;
129 + opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>;
130 + opp-supported-hw = <0x1>;
131 + clock-latency-ns = <100000>;
136 + opp-hz = /bits/ 64 <1200000000>;
137 + opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>;
138 + opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>;
139 + opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>;
140 + opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>;
141 + opp-supported-hw = <0x1>;
142 + clock-latency-ns = <100000>;
147 + opp-hz = /bits/ 64 <1400000000>;
148 + opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>;
149 + opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>;
150 + opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>;
151 + opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>;
152 + opp-supported-hw = <0x1>;
153 + clock-latency-ns = <100000>;
160 + polling-delay-passive = <0>;
161 + polling-delay = <0>;
162 + thermal-sensors = <&tsens 0>;
166 + temperature = <105000>;
167 + hysteresis = <2000>;
172 + temperature = <95000>;
173 + hysteresis = <2000>;
180 + polling-delay-passive = <0>;
181 + polling-delay = <0>;
182 + thermal-sensors = <&tsens 1>;
186 + temperature = <105000>;
187 + hysteresis = <2000>;
192 + temperature = <95000>;
193 + hysteresis = <2000>;
200 + polling-delay-passive = <0>;
201 + polling-delay = <0>;
202 + thermal-sensors = <&tsens 2>;
206 + temperature = <105000>;
207 + hysteresis = <2000>;
212 + temperature = <95000>;
213 + hysteresis = <2000>;
220 + polling-delay-passive = <0>;
221 + polling-delay = <0>;
222 + thermal-sensors = <&tsens 3>;
226 + temperature = <105000>;
227 + hysteresis = <2000>;
232 + temperature = <95000>;
233 + hysteresis = <2000>;
240 + polling-delay-passive = <0>;
241 + polling-delay = <0>;
242 + thermal-sensors = <&tsens 4>;
246 + temperature = <105000>;
247 + hysteresis = <2000>;
252 + temperature = <95000>;
253 + hysteresis = <2000>;
260 + polling-delay-passive = <0>;
261 + polling-delay = <0>;
262 + thermal-sensors = <&tsens 5>;
266 + temperature = <105000>;
267 + hysteresis = <2000>;
272 + temperature = <95000>;
273 + hysteresis = <2000>;
280 + polling-delay-passive = <0>;
281 + polling-delay = <0>;
282 + thermal-sensors = <&tsens 6>;
286 + temperature = <105000>;
287 + hysteresis = <2000>;
292 + temperature = <95000>;
293 + hysteresis = <2000>;
300 + polling-delay-passive = <0>;
301 + polling-delay = <0>;
302 + thermal-sensors = <&tsens 7>;
306 + temperature = <105000>;
307 + hysteresis = <2000>;
312 + temperature = <95000>;
313 + hysteresis = <2000>;
320 + polling-delay-passive = <0>;
321 + polling-delay = <0>;
322 + thermal-sensors = <&tsens 8>;
326 + temperature = <105000>;
327 + hysteresis = <2000>;
332 + temperature = <95000>;
333 + hysteresis = <2000>;
340 + polling-delay-passive = <0>;
341 + polling-delay = <0>;
342 + thermal-sensors = <&tsens 9>;
346 + temperature = <105000>;
347 + hysteresis = <2000>;
352 + temperature = <95000>;
353 + hysteresis = <2000>;
359 + tsens_tz_sensor10 {
360 + polling-delay-passive = <0>;
361 + polling-delay = <0>;
362 + thermal-sensors = <&tsens 10>;
366 + temperature = <105000>;
367 + hysteresis = <2000>;
372 + temperature = <95000>;
373 + hysteresis = <2000>;
381 device_type = "memory";
388 + compatible = "qcom,fab-scaling";
389 + clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
390 + clock-names = "apps-fab-clk", "ddr-fab-clk";
391 + fab_freq_high = <533000000>;
392 + fab_freq_nominal = <400000000>;
393 + cpu_freq_threshold = <1000000000>;
398 compatible = "qcom,scm-ipq806x", "qcom,scm";
400 reg-names = "lpass-lpaif";
404 + compatible = "qcom,krait-cache", "cache";
406 + qcom,saw = <&saw_l2>;
408 + clocks = <&kraitcc 4>;
409 + clock-names = "l2";
410 + l2-supply = <&smb208_s1a>;
411 + operating-points-v2 = <&opp_table_l2>;
415 + compatible = "qcom,rpm-ipq8064";
416 + reg = <0x108000 0x1000>;
417 + qcom,ipc = <&l2cc 0x8 2>;
419 + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
420 + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
421 + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
422 + interrupt-names = "ack", "err", "wakeup";
424 + clocks = <&gcc RPM_MSG_RAM_H_CLK>;
425 + clock-names = "ram";
427 + #address-cells = <1>;
430 + rpmcc: clock-controller {
431 + compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
432 + #clock-cells = <1>;
436 + compatible = "qcom,rpm-smb208-regulators";
439 + regulator-min-microvolt = <1050000>;
440 + regulator-max-microvolt = <1150000>;
442 + qcom,switch-mode-frequency = <1200000>;
446 + regulator-min-microvolt = <1050000>;
447 + regulator-max-microvolt = <1150000>;
449 + qcom,switch-mode-frequency = <1200000>;
453 + regulator-min-microvolt = < 800000>;
454 + regulator-max-microvolt = <1250000>;
456 + qcom,switch-mode-frequency = <1200000>;
460 + regulator-min-microvolt = < 800000>;
461 + regulator-max-microvolt = <1250000>;
463 + qcom,switch-mode-frequency = <1200000>;
469 + compatible = "qcom,prng";
470 + reg = <0x1a500000 0x200>;
471 + clocks = <&gcc PRNG_CLK>;
472 + clock-names = "core";
475 qcom_pinmux: pinmux@800000 {
476 compatible = "qcom,ipq8064-pinctrl";
477 reg = <0x800000 0x4000>;
482 + i2c4_pins: i2c4_pinmux {
484 + pins = "gpio12", "gpio13";
485 + function = "gsbi4";
486 + drive-strength = <12>;
493 pins = "gpio18", "gpio19", "gpio21";
498 + nand_pins: nand_pins {
500 + pins = "gpio34", "gpio35", "gpio36",
501 + "gpio37", "gpio38";
503 + drive-strength = <10>;
510 + drive-strength = <10>;
515 + pins = "gpio40", "gpio41", "gpio42",
516 + "gpio43", "gpio44", "gpio45",
517 + "gpio46", "gpio47";
519 + drive-strength = <10>;
524 + mdio0_pins: mdio0_pins {
526 + pins = "gpio0", "gpio1";
528 + drive-strength = <8>;
533 + rgmii2_pins: rgmii2_pins {
535 + pins = "gpio27", "gpio28", "gpio29",
536 + "gpio30", "gpio31", "gpio32",
537 + "gpio51", "gpio52", "gpio59",
538 + "gpio60", "gpio61", "gpio62";
539 + function = "rgmii2";
540 + drive-strength = <8>;
545 leds_pins: leds_pins {
547 pins = "gpio7", "gpio8", "gpio9",
549 clock-output-names = "acpu1_aux";
552 + l2cc: clock-controller@2011000 {
553 + compatible = "qcom,kpss-gcc", "syscon";
554 + reg = <0x2011000 0x1000>;
555 + clock-output-names = "acpu_l2_aux";
558 + kraitcc: clock-controller {
559 + compatible = "qcom,krait-cc-v1";
560 + #clock-cells = <1>;
563 saw0: regulator@2089000 {
564 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
565 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
570 + saw_l2: regulator@02012000 {
571 + compatible = "qcom,saw2", "syscon";
572 + reg = <0x02012000 0x1000>;
576 + sic_non_secure: sic-non-secure@12100000 {
577 + compatible = "syscon";
578 + reg = <0x12100000 0x10000>;
581 + gsbi1: gsbi@12440000 {
582 + compatible = "qcom,gsbi-v1.0.0";
584 + reg = <0x12440000 0x100>;
585 + clocks = <&gcc GSBI1_H_CLK>;
586 + clock-names = "iface";
587 + #address-cells = <1>;
590 + status = "disabled";
592 + syscon-tcsr = <&tcsr>;
594 + gsbi1_serial: serial@12450000 {
595 + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
596 + reg = <0x12450000 0x100>,
598 + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
599 + clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
600 + clock-names = "core", "iface";
601 + status = "disabled";
604 + gsbi1_i2c: i2c@12460000 {
605 + compatible = "qcom,i2c-qup-v1.1.1";
606 + reg = <0x12460000 0x1000>;
607 + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
608 + clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
609 + clock-names = "core", "iface";
610 + #address-cells = <1>;
612 + status = "disabled";
616 gsbi2: gsbi@12480000 {
617 compatible = "qcom,gsbi-v1.0.0";
623 + gsbi6: gsbi@16500000 {
624 + status = "disabled";
625 + compatible = "qcom,gsbi-v1.0.0";
627 + reg = <0x16500000 0x100>;
628 + clocks = <&gcc GSBI6_H_CLK>;
629 + clock-names = "iface";
630 + #address-cells = <1>;
634 + syscon-tcsr = <&tcsr>;
636 + gsbi6_i2c: i2c@16580000 {
637 + compatible = "qcom,i2c-qup-v1.1.1";
638 + reg = <0x16580000 0x1000>;
639 + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
641 + clocks = <&gcc GSBI6_QUP_CLK>, <&gcc GSBI6_H_CLK>;
642 + clock-names = "core", "iface";
643 + status = "disabled";
645 + #address-cells = <1>;
650 gsbi7: gsbi@16600000 {
652 compatible = "qcom,gsbi-v1.0.0";
654 clock-names = "core", "iface";
658 + gsbi7_i2c: i2c@16680000 {
659 + compatible = "qcom,i2c-qup-v1.1.1";
660 + reg = <0x16680000 0x1000>;
661 + interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
663 + clocks = <&gcc GSBI7_QUP_CLK>, <&gcc GSBI7_H_CLK>;
664 + clock-names = "core", "iface";
665 + status = "disabled";
667 + #address-cells = <1>;
672 sata_phy: sata-phy@1b400000 {
673 @@ -478,6 +1060,95 @@
677 + sfpb_mutex_block: syscon@1200600 {
678 + compatible = "syscon";
679 + reg = <0x01200600 0x100>;
682 + hs_phy_0: hs_phy_0 {
683 + compatible = "qcom,ipq806x-usb-phy-hs";
684 + reg = <0x110f8800 0x30>;
685 + clocks = <&gcc USB30_0_UTMI_CLK>;
686 + clock-names = "ref";
690 + ss_phy_0: ss_phy_0 {
691 + compatible = "qcom,ipq806x-usb-phy-ss";
692 + reg = <0x110f8830 0x30>;
693 + clocks = <&gcc USB30_0_MASTER_CLK>;
694 + clock-names = "ref";
698 + usb3_0: usb3@110f8800 {
699 + compatible = "qcom,dwc3", "syscon";
700 + #address-cells = <1>;
702 + reg = <0x110f8800 0x8000>;
703 + clocks = <&gcc USB30_0_MASTER_CLK>;
704 + clock-names = "core";
708 + resets = <&gcc USB30_0_MASTER_RESET>;
709 + reset-names = "master";
711 + status = "disabled";
713 + dwc3_0: dwc3@11000000 {
714 + compatible = "snps,dwc3";
715 + reg = <0x11000000 0xcd00>;
716 + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
717 + phys = <&hs_phy_0>, <&ss_phy_0>;
718 + phy-names = "usb2-phy", "usb3-phy";
720 + snps,dis_u3_susphy_quirk;
724 + hs_phy_1: hs_phy_1 {
725 + compatible = "qcom,ipq806x-usb-phy-hs";
726 + reg = <0x100f8800 0x30>;
727 + clocks = <&gcc USB30_1_UTMI_CLK>;
728 + clock-names = "ref";
732 + ss_phy_1: ss_phy_1 {
733 + compatible = "qcom,ipq806x-usb-phy-ss";
734 + reg = <0x100f8830 0x30>;
735 + clocks = <&gcc USB30_1_MASTER_CLK>;
736 + clock-names = "ref";
740 + usb3_1: usb3@100f8800 {
741 + compatible = "qcom,dwc3", "syscon";
742 + #address-cells = <1>;
744 + reg = <0x100f8800 0x8000>;
745 + clocks = <&gcc USB30_1_MASTER_CLK>;
746 + clock-names = "core";
750 + resets = <&gcc USB30_1_MASTER_RESET>;
751 + reset-names = "master";
753 + status = "disabled";
755 + dwc3_1: dwc3@10000000 {
756 + compatible = "snps,dwc3";
757 + reg = <0x10000000 0xcd00>;
758 + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
759 + phys = <&hs_phy_1>, <&ss_phy_1>;
760 + phy-names = "usb2-phy", "usb3-phy";
762 + snps,dis_u3_susphy_quirk;
766 pcie0: pci@1b500000 {
767 compatible = "qcom,pcie-ipq8064";
768 reg = <0x1b500000 0x1000
769 @@ -739,6 +1410,59 @@
773 + adm_dma: dma@18300000 {
774 + compatible = "qcom,adm";
775 + reg = <0x18300000 0x100000>;
776 + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
779 + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
780 + clock-names = "core", "iface";
782 + resets = <&gcc ADM0_RESET>,
783 + <&gcc ADM0_PBUS_RESET>,
784 + <&gcc ADM0_C0_RESET>,
785 + <&gcc ADM0_C1_RESET>,
786 + <&gcc ADM0_C2_RESET>;
787 + reset-names = "clk", "pbus", "c0", "c1", "c2";
790 + status = "disabled";
793 + nand_controller: nand-controller@1ac00000 {
794 + compatible = "qcom,ipq806x-nand";
795 + reg = <0x1ac00000 0x800>;
797 + clocks = <&gcc EBI2_CLK>,
798 + <&gcc EBI2_AON_CLK>;
799 + clock-names = "core", "aon";
801 + dmas = <&adm_dma 3>;
802 + dma-names = "rxtx";
803 + qcom,cmd-crci = <15>;
804 + qcom,data-crci = <3>;
806 + status = "disabled";
808 + #address-cells = <1>;
812 + mdio0: mdio@37000000 {
813 + #address-cells = <1>;
816 + compatible = "qcom,ipq8064-mdio", "syscon";
817 + reg = <0x37000000 0x200000>;
818 + resets = <&gcc GMAC_CORE1_RESET>;
819 + reset-names = "stmmaceth";
820 + clocks = <&gcc GMAC_CORE1_CLK>;
821 + clock-names = "stmmaceth";
823 + status = "disabled";
826 vsdcc_fixed: vsdcc-regulator {
827 compatible = "regulator-fixed";
828 regulator-name = "SDCC Power";
829 @@ -814,4 +1538,17 @@
834 + sfpb_mutex: sfpb-mutex {
835 + compatible = "qcom,sfpb-mutex";
836 + syscon = <&sfpb_mutex_block 4 4>;
838 + #hwlock-cells = <1>;
842 + compatible = "qcom,smem";
843 + memory-region = <&smem>;
844 + hwlocks = <&sfpb_mutex 3>;