1 From 5c9f8c2dbdbe53818bcde6aa6695e1331e5f841f Mon Sep 17 00:00:00 2001
2 From: Jonathan McDowell <noodles@earth.li>
3 Date: Sat, 14 Nov 2020 14:02:33 +0000
4 Subject: dmaengine: qcom: Add ADM driver
6 Add the DMA engine driver for the QCOM Application Data Mover (ADM) DMA
7 controller found in the MSM8x60 and IPQ/APQ8064 platforms.
9 The ADM supports both memory to memory transactions and memory
10 to/from peripheral device transactions. The controller also provides
11 flow control capabilities for transactions to/from peripheral devices.
13 The initial release of this driver supports slave transfers to/from
14 peripherals and also incorporates CRCI (client rate control interface)
17 The hardware only supports a 32 bit physical address, so specifying
18 !PHYS_ADDR_T_64BIT gives maximum COMPILE_TEST coverage without having to
19 spend effort on kludging things in the code that will never actually be
20 needed on real hardware.
22 Signed-off-by: Andy Gross <agross@codeaurora.org>
23 Signed-off-by: Thomas Pedersen <twp@codeaurora.org>
24 Signed-off-by: Jonathan McDowell <noodles@earth.li>
25 Link: https://lore.kernel.org/r/20201114140233.GM32650@earth.li
26 Signed-off-by: Vinod Koul <vkoul@kernel.org>
28 drivers/dma/qcom/Kconfig | 11 +
29 drivers/dma/qcom/Makefile | 1 +
30 drivers/dma/qcom/qcom_adm.c | 903 ++++++++++++++++++++++++++++++++++++++++++++
31 3 files changed, 915 insertions(+)
32 create mode 100644 drivers/dma/qcom/qcom_adm.c
34 diff --git a/drivers/dma/qcom/Kconfig b/drivers/dma/qcom/Kconfig
35 index 3bcb689162c67..0389d60d2604a 100644
36 --- a/drivers/dma/qcom/Kconfig
37 +++ b/drivers/dma/qcom/Kconfig
39 # SPDX-License-Identifier: GPL-2.0-only
41 + tristate "Qualcomm ADM support"
42 + depends on (ARCH_QCOM || COMPILE_TEST) && !PHYS_ADDR_T_64BIT
44 + select DMA_VIRTUAL_CHANNELS
46 + Enable support for the Qualcomm Application Data Mover (ADM) DMA
47 + controller, as present on MSM8x60, APQ8064, and IPQ8064 devices.
48 + This controller provides DMA capabilities for both general purpose
49 + and on-chip peripheral devices.
52 tristate "QCOM BAM DMA support"
53 depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM)
54 diff --git a/drivers/dma/qcom/Makefile b/drivers/dma/qcom/Makefile
55 index 1ae92da88b0c9..346e643fbb6db 100644
56 --- a/drivers/dma/qcom/Makefile
57 +++ b/drivers/dma/qcom/Makefile
59 # SPDX-License-Identifier: GPL-2.0
60 +obj-$(CONFIG_QCOM_ADM) += qcom_adm.o
61 obj-$(CONFIG_QCOM_BAM_DMA) += bam_dma.o
62 obj-$(CONFIG_QCOM_HIDMA_MGMT) += hdma_mgmt.o
63 hdma_mgmt-objs := hidma_mgmt.o hidma_mgmt_sys.o
64 diff --git a/drivers/dma/qcom/qcom_adm.c b/drivers/dma/qcom/qcom_adm.c
66 index 0000000000000..9b6f8e050ecce
68 +++ b/drivers/dma/qcom/qcom_adm.c
70 +// SPDX-License-Identifier: GPL-2.0-only
72 + * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
75 +#include <linux/clk.h>
76 +#include <linux/delay.h>
77 +#include <linux/device.h>
78 +#include <linux/dmaengine.h>
79 +#include <linux/dma-mapping.h>
80 +#include <linux/init.h>
81 +#include <linux/interrupt.h>
82 +#include <linux/io.h>
83 +#include <linux/kernel.h>
84 +#include <linux/module.h>
85 +#include <linux/of.h>
86 +#include <linux/of_address.h>
87 +#include <linux/of_irq.h>
88 +#include <linux/of_dma.h>
89 +#include <linux/platform_device.h>
90 +#include <linux/reset.h>
91 +#include <linux/scatterlist.h>
92 +#include <linux/slab.h>
94 +#include "../dmaengine.h"
95 +#include "../virt-dma.h"
97 +/* ADM registers - calculated from channel number and security domain */
98 +#define ADM_CHAN_MULTI 0x4
99 +#define ADM_CI_MULTI 0x4
100 +#define ADM_CRCI_MULTI 0x4
101 +#define ADM_EE_MULTI 0x800
102 +#define ADM_CHAN_OFFS(chan) (ADM_CHAN_MULTI * (chan))
103 +#define ADM_EE_OFFS(ee) (ADM_EE_MULTI * (ee))
104 +#define ADM_CHAN_EE_OFFS(chan, ee) (ADM_CHAN_OFFS(chan) + ADM_EE_OFFS(ee))
105 +#define ADM_CHAN_OFFS(chan) (ADM_CHAN_MULTI * (chan))
106 +#define ADM_CI_OFFS(ci) (ADM_CHAN_OFF(ci))
107 +#define ADM_CH_CMD_PTR(chan, ee) (ADM_CHAN_EE_OFFS(chan, ee))
108 +#define ADM_CH_RSLT(chan, ee) (0x40 + ADM_CHAN_EE_OFFS(chan, ee))
109 +#define ADM_CH_FLUSH_STATE0(chan, ee) (0x80 + ADM_CHAN_EE_OFFS(chan, ee))
110 +#define ADM_CH_STATUS_SD(chan, ee) (0x200 + ADM_CHAN_EE_OFFS(chan, ee))
111 +#define ADM_CH_CONF(chan) (0x240 + ADM_CHAN_OFFS(chan))
112 +#define ADM_CH_RSLT_CONF(chan, ee) (0x300 + ADM_CHAN_EE_OFFS(chan, ee))
113 +#define ADM_SEC_DOMAIN_IRQ_STATUS(ee) (0x380 + ADM_EE_OFFS(ee))
114 +#define ADM_CI_CONF(ci) (0x390 + (ci) * ADM_CI_MULTI)
115 +#define ADM_GP_CTL 0x3d8
116 +#define ADM_CRCI_CTL(crci, ee) (0x400 + (crci) * ADM_CRCI_MULTI + \
119 +/* channel status */
120 +#define ADM_CH_STATUS_VALID BIT(1)
122 +/* channel result */
123 +#define ADM_CH_RSLT_VALID BIT(31)
124 +#define ADM_CH_RSLT_ERR BIT(3)
125 +#define ADM_CH_RSLT_FLUSH BIT(2)
126 +#define ADM_CH_RSLT_TPD BIT(1)
129 +#define ADM_CH_CONF_SHADOW_EN BIT(12)
130 +#define ADM_CH_CONF_MPU_DISABLE BIT(11)
131 +#define ADM_CH_CONF_PERM_MPU_CONF BIT(9)
132 +#define ADM_CH_CONF_FORCE_RSLT_EN BIT(7)
133 +#define ADM_CH_CONF_SEC_DOMAIN(ee) ((((ee) & 0x3) << 4) | (((ee) & 0x4) << 11))
135 +/* channel result conf */
136 +#define ADM_CH_RSLT_CONF_FLUSH_EN BIT(1)
137 +#define ADM_CH_RSLT_CONF_IRQ_EN BIT(0)
140 +#define ADM_CRCI_CTL_MUX_SEL BIT(18)
141 +#define ADM_CRCI_CTL_RST BIT(17)
143 +/* CI configuration */
144 +#define ADM_CI_RANGE_END(x) ((x) << 24)
145 +#define ADM_CI_RANGE_START(x) ((x) << 16)
146 +#define ADM_CI_BURST_4_WORDS BIT(2)
147 +#define ADM_CI_BURST_8_WORDS BIT(3)
150 +#define ADM_GP_CTL_LP_EN BIT(12)
151 +#define ADM_GP_CTL_LP_CNT(x) ((x) << 8)
153 +/* Command pointer list entry */
154 +#define ADM_CPLE_LP BIT(31)
155 +#define ADM_CPLE_CMD_PTR_LIST BIT(29)
157 +/* Command list entry */
158 +#define ADM_CMD_LC BIT(31)
159 +#define ADM_CMD_DST_CRCI(n) (((n) & 0xf) << 7)
160 +#define ADM_CMD_SRC_CRCI(n) (((n) & 0xf) << 3)
162 +#define ADM_CMD_TYPE_SINGLE 0x0
163 +#define ADM_CMD_TYPE_BOX 0x3
165 +#define ADM_CRCI_MUX_SEL BIT(4)
166 +#define ADM_DESC_ALIGN 8
167 +#define ADM_MAX_XFER (SZ_64K - 1)
168 +#define ADM_MAX_ROWS (SZ_64K - 1)
169 +#define ADM_MAX_CHANNELS 16
171 +struct adm_desc_hw_box {
180 +struct adm_desc_hw_single {
187 +struct adm_async_desc {
188 + struct virt_dma_desc vd;
189 + struct adm_device *adev;
192 + enum dma_transfer_direction dir;
193 + dma_addr_t dma_addr;
197 + dma_addr_t cp_addr;
204 + struct virt_dma_chan vc;
205 + struct adm_device *adev;
207 + /* parsed from DT */
208 + u32 id; /* channel id */
210 + struct adm_async_desc *curr_txd;
211 + struct dma_slave_config slave;
212 + struct list_head node;
218 +static inline struct adm_chan *to_adm_chan(struct dma_chan *common)
220 + return container_of(common, struct adm_chan, vc.chan);
224 + void __iomem *regs;
225 + struct device *dev;
226 + struct dma_device common;
227 + struct device_dma_parameters dma_parms;
228 + struct adm_chan *channels;
232 + struct clk *core_clk;
233 + struct clk *iface_clk;
235 + struct reset_control *clk_reset;
236 + struct reset_control *c0_reset;
237 + struct reset_control *c1_reset;
238 + struct reset_control *c2_reset;
243 + * adm_free_chan - Frees dma resources associated with the specific channel
245 + * Free all allocated descriptors associated with this channel
248 +static void adm_free_chan(struct dma_chan *chan)
250 + /* free all queued descriptors */
251 + vchan_free_chan_resources(to_virt_chan(chan));
255 + * adm_get_blksize - Get block size from burst value
258 +static int adm_get_blksize(unsigned int burst)
267 + ret = ffs(burst >> 4) - 1;
284 + * adm_process_fc_descriptors - Process descriptors for flow controlled xfers
286 + * @achan: ADM channel
287 + * @desc: Descriptor memory pointer
288 + * @sg: Scatterlist entry
289 + * @crci: CRCI value
290 + * @burst: Burst size of transaction
291 + * @direction: DMA transfer direction
293 +static void *adm_process_fc_descriptors(struct adm_chan *achan, void *desc,
294 + struct scatterlist *sg, u32 crci,
296 + enum dma_transfer_direction direction)
298 + struct adm_desc_hw_box *box_desc = NULL;
299 + struct adm_desc_hw_single *single_desc;
300 + u32 remainder = sg_dma_len(sg);
301 + u32 rows, row_offset, crci_cmd;
302 + u32 mem_addr = sg_dma_address(sg);
303 + u32 *incr_addr = &mem_addr;
306 + if (direction == DMA_DEV_TO_MEM) {
307 + crci_cmd = ADM_CMD_SRC_CRCI(crci);
308 + row_offset = burst;
309 + src = &achan->slave.src_addr;
312 + crci_cmd = ADM_CMD_DST_CRCI(crci);
313 + row_offset = burst << 16;
315 + dst = &achan->slave.dst_addr;
318 + while (remainder >= burst) {
320 + box_desc->cmd = ADM_CMD_TYPE_BOX | crci_cmd;
321 + box_desc->row_offset = row_offset;
322 + box_desc->src_addr = *src;
323 + box_desc->dst_addr = *dst;
325 + rows = remainder / burst;
326 + rows = min_t(u32, rows, ADM_MAX_ROWS);
327 + box_desc->num_rows = rows << 16 | rows;
328 + box_desc->row_len = burst << 16 | burst;
330 + *incr_addr += burst * rows;
331 + remainder -= burst * rows;
332 + desc += sizeof(*box_desc);
335 + /* if leftover bytes, do one single descriptor */
337 + single_desc = desc;
338 + single_desc->cmd = ADM_CMD_TYPE_SINGLE | crci_cmd;
339 + single_desc->len = remainder;
340 + single_desc->src_addr = *src;
341 + single_desc->dst_addr = *dst;
342 + desc += sizeof(*single_desc);
344 + if (sg_is_last(sg))
345 + single_desc->cmd |= ADM_CMD_LC;
347 + if (box_desc && sg_is_last(sg))
348 + box_desc->cmd |= ADM_CMD_LC;
355 + * adm_process_non_fc_descriptors - Process descriptors for non-fc xfers
357 + * @achan: ADM channel
358 + * @desc: Descriptor memory pointer
359 + * @sg: Scatterlist entry
360 + * @direction: DMA transfer direction
362 +static void *adm_process_non_fc_descriptors(struct adm_chan *achan, void *desc,
363 + struct scatterlist *sg,
364 + enum dma_transfer_direction direction)
366 + struct adm_desc_hw_single *single_desc;
367 + u32 remainder = sg_dma_len(sg);
368 + u32 mem_addr = sg_dma_address(sg);
369 + u32 *incr_addr = &mem_addr;
372 + if (direction == DMA_DEV_TO_MEM) {
373 + src = &achan->slave.src_addr;
377 + dst = &achan->slave.dst_addr;
381 + single_desc = desc;
382 + single_desc->cmd = ADM_CMD_TYPE_SINGLE;
383 + single_desc->src_addr = *src;
384 + single_desc->dst_addr = *dst;
385 + single_desc->len = (remainder > ADM_MAX_XFER) ?
386 + ADM_MAX_XFER : remainder;
388 + remainder -= single_desc->len;
389 + *incr_addr += single_desc->len;
390 + desc += sizeof(*single_desc);
391 + } while (remainder);
393 + /* set last command if this is the end of the whole transaction */
394 + if (sg_is_last(sg))
395 + single_desc->cmd |= ADM_CMD_LC;
401 + * adm_prep_slave_sg - Prep slave sg transaction
403 + * @chan: dma channel
404 + * @sgl: scatter gather list
405 + * @sg_len: length of sg
406 + * @direction: DMA transfer direction
407 + * @flags: DMA flags
408 + * @context: transfer context (unused)
410 +static struct dma_async_tx_descriptor *adm_prep_slave_sg(struct dma_chan *chan,
411 + struct scatterlist *sgl,
412 + unsigned int sg_len,
413 + enum dma_transfer_direction direction,
414 + unsigned long flags,
417 + struct adm_chan *achan = to_adm_chan(chan);
418 + struct adm_device *adev = achan->adev;
419 + struct adm_async_desc *async_desc;
420 + struct scatterlist *sg;
421 + dma_addr_t cple_addr;
423 + u32 single_count = 0, box_count = 0, crci = 0;
428 + if (!is_slave_direction(direction)) {
429 + dev_err(adev->dev, "invalid dma direction\n");
434 + * get burst value from slave configuration
436 + burst = (direction == DMA_MEM_TO_DEV) ?
437 + achan->slave.dst_maxburst :
438 + achan->slave.src_maxburst;
440 + /* if using flow control, validate burst and crci values */
441 + if (achan->slave.device_fc) {
442 + blk_size = adm_get_blksize(burst);
443 + if (blk_size < 0) {
444 + dev_err(adev->dev, "invalid burst value: %d\n",
446 + return ERR_PTR(-EINVAL);
449 + crci = achan->slave.slave_id & 0xf;
450 + if (!crci || achan->slave.slave_id > 0x1f) {
451 + dev_err(adev->dev, "invalid crci value\n");
452 + return ERR_PTR(-EINVAL);
456 + /* iterate through sgs and compute allocation size of structures */
457 + for_each_sg(sgl, sg, sg_len, i) {
458 + if (achan->slave.device_fc) {
459 + box_count += DIV_ROUND_UP(sg_dma_len(sg) / burst,
461 + if (sg_dma_len(sg) % burst)
464 + single_count += DIV_ROUND_UP(sg_dma_len(sg),
469 + async_desc = kzalloc(sizeof(*async_desc), GFP_NOWAIT);
471 + return ERR_PTR(-ENOMEM);
474 + async_desc->mux = achan->slave.slave_id & ADM_CRCI_MUX_SEL ?
475 + ADM_CRCI_CTL_MUX_SEL : 0;
476 + async_desc->crci = crci;
477 + async_desc->blk_size = blk_size;
478 + async_desc->dma_len = single_count * sizeof(struct adm_desc_hw_single) +
479 + box_count * sizeof(struct adm_desc_hw_box) +
480 + sizeof(*cple) + 2 * ADM_DESC_ALIGN;
482 + async_desc->cpl = kzalloc(async_desc->dma_len, GFP_NOWAIT);
483 + if (!async_desc->cpl)
486 + async_desc->adev = adev;
488 + /* both command list entry and descriptors must be 8 byte aligned */
489 + cple = PTR_ALIGN(async_desc->cpl, ADM_DESC_ALIGN);
490 + desc = PTR_ALIGN(cple + 1, ADM_DESC_ALIGN);
492 + for_each_sg(sgl, sg, sg_len, i) {
493 + async_desc->length += sg_dma_len(sg);
495 + if (achan->slave.device_fc)
496 + desc = adm_process_fc_descriptors(achan, desc, sg, crci,
499 + desc = adm_process_non_fc_descriptors(achan, desc, sg,
503 + async_desc->dma_addr = dma_map_single(adev->dev, async_desc->cpl,
504 + async_desc->dma_len,
506 + if (dma_mapping_error(adev->dev, async_desc->dma_addr))
509 + cple_addr = async_desc->dma_addr + ((void *)cple - async_desc->cpl);
511 + /* init cmd list */
512 + dma_sync_single_for_cpu(adev->dev, cple_addr, sizeof(*cple),
514 + *cple = ADM_CPLE_LP;
515 + *cple |= (async_desc->dma_addr + ADM_DESC_ALIGN) >> 3;
516 + dma_sync_single_for_device(adev->dev, cple_addr, sizeof(*cple),
519 + return vchan_tx_prep(&achan->vc, &async_desc->vd, flags);
523 + return ERR_PTR(-ENOMEM);
527 + * adm_terminate_all - terminate all transactions on a channel
528 + * @achan: adm dma channel
530 + * Dequeues and frees all transactions, aborts current transaction
531 + * No callbacks are done
534 +static int adm_terminate_all(struct dma_chan *chan)
536 + struct adm_chan *achan = to_adm_chan(chan);
537 + struct adm_device *adev = achan->adev;
538 + unsigned long flags;
541 + spin_lock_irqsave(&achan->vc.lock, flags);
542 + vchan_get_all_descriptors(&achan->vc, &head);
544 + /* send flush command to terminate current transaction */
545 + writel_relaxed(0x0,
546 + adev->regs + ADM_CH_FLUSH_STATE0(achan->id, adev->ee));
548 + spin_unlock_irqrestore(&achan->vc.lock, flags);
550 + vchan_dma_desc_free_list(&achan->vc, &head);
555 +static int adm_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg)
557 + struct adm_chan *achan = to_adm_chan(chan);
558 + unsigned long flag;
560 + spin_lock_irqsave(&achan->vc.lock, flag);
561 + memcpy(&achan->slave, cfg, sizeof(struct dma_slave_config));
562 + spin_unlock_irqrestore(&achan->vc.lock, flag);
568 + * adm_start_dma - start next transaction
569 + * @achan - ADM dma channel
571 +static void adm_start_dma(struct adm_chan *achan)
573 + struct virt_dma_desc *vd = vchan_next_desc(&achan->vc);
574 + struct adm_device *adev = achan->adev;
575 + struct adm_async_desc *async_desc;
577 + lockdep_assert_held(&achan->vc.lock);
582 + list_del(&vd->node);
584 + /* write next command list out to the CMD FIFO */
585 + async_desc = container_of(vd, struct adm_async_desc, vd);
586 + achan->curr_txd = async_desc;
588 + /* reset channel error */
591 + if (!achan->initialized) {
592 + /* enable interrupts */
593 + writel(ADM_CH_CONF_SHADOW_EN |
594 + ADM_CH_CONF_PERM_MPU_CONF |
595 + ADM_CH_CONF_MPU_DISABLE |
596 + ADM_CH_CONF_SEC_DOMAIN(adev->ee),
597 + adev->regs + ADM_CH_CONF(achan->id));
599 + writel(ADM_CH_RSLT_CONF_IRQ_EN | ADM_CH_RSLT_CONF_FLUSH_EN,
600 + adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee));
602 + achan->initialized = 1;
605 + /* set the crci block size if this transaction requires CRCI */
606 + if (async_desc->crci) {
607 + writel(async_desc->mux | async_desc->blk_size,
608 + adev->regs + ADM_CRCI_CTL(async_desc->crci, adev->ee));
611 + /* make sure IRQ enable doesn't get reordered */
614 + /* write next command list out to the CMD FIFO */
615 + writel(ALIGN(async_desc->dma_addr, ADM_DESC_ALIGN) >> 3,
616 + adev->regs + ADM_CH_CMD_PTR(achan->id, adev->ee));
620 + * adm_dma_irq - irq handler for ADM controller
621 + * @irq: IRQ of interrupt
622 + * @data: callback data
624 + * IRQ handler for the bam controller
626 +static irqreturn_t adm_dma_irq(int irq, void *data)
628 + struct adm_device *adev = data;
630 + struct adm_async_desc *async_desc;
631 + unsigned long flags;
633 + srcs = readl_relaxed(adev->regs +
634 + ADM_SEC_DOMAIN_IRQ_STATUS(adev->ee));
636 + for (i = 0; i < ADM_MAX_CHANNELS; i++) {
637 + struct adm_chan *achan = &adev->channels[i];
638 + u32 status, result;
640 + if (srcs & BIT(i)) {
641 + status = readl_relaxed(adev->regs +
642 + ADM_CH_STATUS_SD(i, adev->ee));
644 + /* if no result present, skip */
645 + if (!(status & ADM_CH_STATUS_VALID))
648 + result = readl_relaxed(adev->regs +
649 + ADM_CH_RSLT(i, adev->ee));
651 + /* no valid results, skip */
652 + if (!(result & ADM_CH_RSLT_VALID))
655 + /* flag error if transaction was flushed or failed */
656 + if (result & (ADM_CH_RSLT_ERR | ADM_CH_RSLT_FLUSH))
659 + spin_lock_irqsave(&achan->vc.lock, flags);
660 + async_desc = achan->curr_txd;
662 + achan->curr_txd = NULL;
665 + vchan_cookie_complete(&async_desc->vd);
667 + /* kick off next DMA */
668 + adm_start_dma(achan);
671 + spin_unlock_irqrestore(&achan->vc.lock, flags);
675 + return IRQ_HANDLED;
679 + * adm_tx_status - returns status of transaction
680 + * @chan: dma channel
681 + * @cookie: transaction cookie
682 + * @txstate: DMA transaction state
684 + * Return status of dma transaction
686 +static enum dma_status adm_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
687 + struct dma_tx_state *txstate)
689 + struct adm_chan *achan = to_adm_chan(chan);
690 + struct virt_dma_desc *vd;
691 + enum dma_status ret;
692 + unsigned long flags;
693 + size_t residue = 0;
695 + ret = dma_cookie_status(chan, cookie, txstate);
696 + if (ret == DMA_COMPLETE || !txstate)
699 + spin_lock_irqsave(&achan->vc.lock, flags);
701 + vd = vchan_find_desc(&achan->vc, cookie);
703 + residue = container_of(vd, struct adm_async_desc, vd)->length;
705 + spin_unlock_irqrestore(&achan->vc.lock, flags);
708 + * residue is either the full length if it is in the issued list, or 0
709 + * if it is in progress. We have no reliable way of determining
710 + * anything inbetween
712 + dma_set_residue(txstate, residue);
721 + * adm_issue_pending - starts pending transactions
722 + * @chan: dma channel
724 + * Issues all pending transactions and starts DMA
726 +static void adm_issue_pending(struct dma_chan *chan)
728 + struct adm_chan *achan = to_adm_chan(chan);
729 + unsigned long flags;
731 + spin_lock_irqsave(&achan->vc.lock, flags);
733 + if (vchan_issue_pending(&achan->vc) && !achan->curr_txd)
734 + adm_start_dma(achan);
735 + spin_unlock_irqrestore(&achan->vc.lock, flags);
739 + * adm_dma_free_desc - free descriptor memory
740 + * @vd: virtual descriptor
743 +static void adm_dma_free_desc(struct virt_dma_desc *vd)
745 + struct adm_async_desc *async_desc = container_of(vd,
746 + struct adm_async_desc, vd);
748 + dma_unmap_single(async_desc->adev->dev, async_desc->dma_addr,
749 + async_desc->dma_len, DMA_TO_DEVICE);
750 + kfree(async_desc->cpl);
754 +static void adm_channel_init(struct adm_device *adev, struct adm_chan *achan,
758 + achan->adev = adev;
760 + vchan_init(&achan->vc, &adev->common);
761 + achan->vc.desc_free = adm_dma_free_desc;
764 +static int adm_dma_probe(struct platform_device *pdev)
766 + struct adm_device *adev;
770 + adev = devm_kzalloc(&pdev->dev, sizeof(*adev), GFP_KERNEL);
774 + adev->dev = &pdev->dev;
776 + adev->regs = devm_platform_ioremap_resource(pdev, 0);
777 + if (IS_ERR(adev->regs))
778 + return PTR_ERR(adev->regs);
780 + adev->irq = platform_get_irq(pdev, 0);
784 + ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &adev->ee);
786 + dev_err(adev->dev, "Execution environment unspecified\n");
790 + adev->core_clk = devm_clk_get(adev->dev, "core");
791 + if (IS_ERR(adev->core_clk))
792 + return PTR_ERR(adev->core_clk);
794 + adev->iface_clk = devm_clk_get(adev->dev, "iface");
795 + if (IS_ERR(adev->iface_clk))
796 + return PTR_ERR(adev->iface_clk);
798 + adev->clk_reset = devm_reset_control_get_exclusive(&pdev->dev, "clk");
799 + if (IS_ERR(adev->clk_reset)) {
800 + dev_err(adev->dev, "failed to get ADM0 reset\n");
801 + return PTR_ERR(adev->clk_reset);
804 + adev->c0_reset = devm_reset_control_get_exclusive(&pdev->dev, "c0");
805 + if (IS_ERR(adev->c0_reset)) {
806 + dev_err(adev->dev, "failed to get ADM0 C0 reset\n");
807 + return PTR_ERR(adev->c0_reset);
810 + adev->c1_reset = devm_reset_control_get_exclusive(&pdev->dev, "c1");
811 + if (IS_ERR(adev->c1_reset)) {
812 + dev_err(adev->dev, "failed to get ADM0 C1 reset\n");
813 + return PTR_ERR(adev->c1_reset);
816 + adev->c2_reset = devm_reset_control_get_exclusive(&pdev->dev, "c2");
817 + if (IS_ERR(adev->c2_reset)) {
818 + dev_err(adev->dev, "failed to get ADM0 C2 reset\n");
819 + return PTR_ERR(adev->c2_reset);
822 + ret = clk_prepare_enable(adev->core_clk);
824 + dev_err(adev->dev, "failed to prepare/enable core clock\n");
828 + ret = clk_prepare_enable(adev->iface_clk);
830 + dev_err(adev->dev, "failed to prepare/enable iface clock\n");
831 + goto err_disable_core_clk;
834 + reset_control_assert(adev->clk_reset);
835 + reset_control_assert(adev->c0_reset);
836 + reset_control_assert(adev->c1_reset);
837 + reset_control_assert(adev->c2_reset);
841 + reset_control_deassert(adev->clk_reset);
842 + reset_control_deassert(adev->c0_reset);
843 + reset_control_deassert(adev->c1_reset);
844 + reset_control_deassert(adev->c2_reset);
846 + adev->channels = devm_kcalloc(adev->dev, ADM_MAX_CHANNELS,
847 + sizeof(*adev->channels), GFP_KERNEL);
849 + if (!adev->channels) {
851 + goto err_disable_clks;
854 + /* allocate and initialize channels */
855 + INIT_LIST_HEAD(&adev->common.channels);
857 + for (i = 0; i < ADM_MAX_CHANNELS; i++)
858 + adm_channel_init(adev, &adev->channels[i], i);
861 + for (i = 0; i < 16; i++)
862 + writel(ADM_CRCI_CTL_RST, adev->regs +
863 + ADM_CRCI_CTL(i, adev->ee));
865 + /* configure client interfaces */
866 + writel(ADM_CI_RANGE_START(0x40) | ADM_CI_RANGE_END(0xb0) |
867 + ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(0));
868 + writel(ADM_CI_RANGE_START(0x2a) | ADM_CI_RANGE_END(0x2c) |
869 + ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(1));
870 + writel(ADM_CI_RANGE_START(0x12) | ADM_CI_RANGE_END(0x28) |
871 + ADM_CI_BURST_8_WORDS, adev->regs + ADM_CI_CONF(2));
872 + writel(ADM_GP_CTL_LP_EN | ADM_GP_CTL_LP_CNT(0xf),
873 + adev->regs + ADM_GP_CTL);
875 + ret = devm_request_irq(adev->dev, adev->irq, adm_dma_irq,
876 + 0, "adm_dma", adev);
878 + goto err_disable_clks;
880 + platform_set_drvdata(pdev, adev);
882 + adev->common.dev = adev->dev;
883 + adev->common.dev->dma_parms = &adev->dma_parms;
885 + /* set capabilities */
886 + dma_cap_zero(adev->common.cap_mask);
887 + dma_cap_set(DMA_SLAVE, adev->common.cap_mask);
888 + dma_cap_set(DMA_PRIVATE, adev->common.cap_mask);
890 + /* initialize dmaengine apis */
891 + adev->common.directions = BIT(DMA_DEV_TO_MEM | DMA_MEM_TO_DEV);
892 + adev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
893 + adev->common.src_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
894 + adev->common.dst_addr_widths = DMA_SLAVE_BUSWIDTH_4_BYTES;
895 + adev->common.device_free_chan_resources = adm_free_chan;
896 + adev->common.device_prep_slave_sg = adm_prep_slave_sg;
897 + adev->common.device_issue_pending = adm_issue_pending;
898 + adev->common.device_tx_status = adm_tx_status;
899 + adev->common.device_terminate_all = adm_terminate_all;
900 + adev->common.device_config = adm_slave_config;
902 + ret = dma_async_device_register(&adev->common);
904 + dev_err(adev->dev, "failed to register dma async device\n");
905 + goto err_disable_clks;
908 + ret = of_dma_controller_register(pdev->dev.of_node,
909 + of_dma_xlate_by_chan_id,
912 + goto err_unregister_dma;
917 + dma_async_device_unregister(&adev->common);
919 + clk_disable_unprepare(adev->iface_clk);
920 +err_disable_core_clk:
921 + clk_disable_unprepare(adev->core_clk);
926 +static int adm_dma_remove(struct platform_device *pdev)
928 + struct adm_device *adev = platform_get_drvdata(pdev);
929 + struct adm_chan *achan;
932 + of_dma_controller_free(pdev->dev.of_node);
933 + dma_async_device_unregister(&adev->common);
935 + for (i = 0; i < ADM_MAX_CHANNELS; i++) {
936 + achan = &adev->channels[i];
938 + /* mask IRQs for this channel/EE pair */
939 + writel(0, adev->regs + ADM_CH_RSLT_CONF(achan->id, adev->ee));
941 + tasklet_kill(&adev->channels[i].vc.task);
942 + adm_terminate_all(&adev->channels[i].vc.chan);
945 + devm_free_irq(adev->dev, adev->irq, adev);
947 + clk_disable_unprepare(adev->core_clk);
948 + clk_disable_unprepare(adev->iface_clk);
953 +static const struct of_device_id adm_of_match[] = {
954 + { .compatible = "qcom,adm", },
957 +MODULE_DEVICE_TABLE(of, adm_of_match);
959 +static struct platform_driver adm_dma_driver = {
960 + .probe = adm_dma_probe,
961 + .remove = adm_dma_remove,
963 + .name = "adm-dma-engine",
964 + .of_match_table = adm_of_match,
968 +module_platform_driver(adm_dma_driver);
970 +MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
971 +MODULE_DESCRIPTION("QCOM ADM DMA engine driver");
972 +MODULE_LICENSE("GPL v2");