1 From 0af44917941cbfecdc86bb9bf05ff01d22a88973 Mon Sep 17 00:00:00 2001
2 From: Ansuel Smith <ansuelsmth@gmail.com>
3 Date: Sun, 7 Feb 2021 16:52:56 +0100
4 Subject: [PATCH 1/4] ipq806x: gcc: add missing clk flag
6 Some flag are missing from the original code.
7 These clk can't be set using the protected-clock proprities as they
8 cause the malfunction of the serial interface.
9 These clks are needed for the rpm interface to work proprely or the
10 cpu regulators starts to fail as soon as they are disabled by the
13 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
15 drivers/clk/qcom/gcc-ipq806x.c | 19 +++++++++++++------
16 1 file changed, 13 insertions(+), 6 deletions(-)
18 --- a/drivers/clk/qcom/gcc-ipq806x.c
19 +++ b/drivers/clk/qcom/gcc-ipq806x.c
20 @@ -65,6 +65,7 @@ static struct clk_pll pll3 = {
21 .parent_names = (const char *[]){ "pxo" },
24 + .flags = CLK_IS_CRITICAL,
28 @@ -782,7 +783,7 @@ static struct clk_rcg gsbi4_qup_src = {
29 .parent_names = gcc_pxo_pll8,
32 - .flags = CLK_SET_PARENT_GATE,
33 + .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
37 @@ -798,7 +799,7 @@ static struct clk_branch gsbi4_qup_clk =
38 .parent_names = (const char *[]){ "gsbi4_qup_src" },
40 .ops = &clk_branch_ops,
41 - .flags = CLK_SET_RATE_PARENT,
42 + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
46 @@ -880,7 +881,7 @@ static struct clk_rcg gsbi6_qup_src = {
47 .parent_names = gcc_pxo_pll8,
50 - .flags = CLK_SET_PARENT_GATE,
51 + .flags = CLK_SET_PARENT_GATE | CLK_IGNORE_UNUSED,
55 @@ -945,7 +946,7 @@ static struct clk_branch gsbi7_qup_clk =
56 .parent_names = (const char *[]){ "gsbi7_qup_src" },
58 .ops = &clk_branch_ops,
59 - .flags = CLK_SET_RATE_PARENT,
60 + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
64 @@ -991,6 +992,7 @@ static struct clk_branch gsbi4_h_clk = {
65 .hw.init = &(struct clk_init_data){
66 .name = "gsbi4_h_clk",
67 .ops = &clk_branch_ops,
68 + .flags = CLK_IGNORE_UNUSED,
72 @@ -1424,6 +1426,7 @@ static struct clk_rcg tsif_ref_src = {
73 .parent_names = gcc_pxo_pll8,
76 + .flags = CLK_SET_RATE_GATE,
80 @@ -2694,7 +2697,8 @@ static struct clk_dyn_rcg ubi32_core1_sr
81 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
83 .ops = &clk_dyn_rcg_ops,
84 - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
85 + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |
90 @@ -2747,7 +2751,8 @@ static struct clk_dyn_rcg ubi32_core2_sr
91 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
93 .ops = &clk_dyn_rcg_ops,
94 - .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
95 + .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE |