1 From 22a0f55b0e505fbbbb680e451a62878bc97f7ff1 Mon Sep 17 00:00:00 2001
2 From: Ansuel Smith <ansuelsmth@gmail.com>
3 Date: Sun, 7 Feb 2021 17:23:38 +0100
4 Subject: [PATCH 4/4] ipq806x: gcc: add missing clk and reset for crypto engine
6 Add missing clk and reset needed for nss additional core and crypto
9 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
11 drivers/clk/qcom/gcc-ipq806x.c | 250 +++++++++++++++++++
12 include/dt-bindings/clock/qcom,gcc-ipq806x.h | 5 +-
13 include/dt-bindings/reset/qcom,gcc-ipq806x.h | 5 +
14 3 files changed, 259 insertions(+), 1 deletion(-)
16 --- a/drivers/clk/qcom/gcc-ipq806x.c
17 +++ b/drivers/clk/qcom/gcc-ipq806x.c
18 @@ -223,7 +223,9 @@ static struct clk_regmap pll14_vote = {
20 static struct pll_freq_tbl pll18_freq_tbl[] = {
21 NSS_PLL_RATE(550000000, 44, 0, 1, 0x01495625),
22 + NSS_PLL_RATE(600000000, 48, 0, 1, 0x01495625),
23 NSS_PLL_RATE(733000000, 58, 16, 25, 0x014b5625),
24 + NSS_PLL_RATE(800000000, 64, 0, 1, 0x01495625),
27 static struct clk_pll pll18 = {
28 @@ -245,6 +247,22 @@ static struct clk_pll pll18 = {
32 +static struct clk_pll pll11 = {
36 + .config_reg = 0x3194,
38 + .status_reg = 0x3198,
40 + .clkr.hw.init = &(struct clk_init_data){
42 + .parent_names = (const char *[]){ "pxo" },
44 + .ops = &clk_pll_ops,
51 @@ -253,6 +271,7 @@ enum {
58 static const struct parent_map gcc_pxo_pll8_map[] = {
59 @@ -320,6 +339,42 @@ static const char * const gcc_pxo_pll8_p
63 +static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
72 +static const char *gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
81 +static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
90 +static const char *gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
99 static struct freq_tbl clk_tbl_gsbi_uart[] = {
100 { 1843200, P_PLL8, 2, 6, 625 },
101 { 3686400, P_PLL8, 2, 12, 625 },
102 @@ -1261,6 +1316,7 @@ static const struct freq_tbl clk_tbl_sdc
103 { 20210000, P_PLL8, 1, 1, 19 },
104 { 24000000, P_PLL8, 4, 1, 4 },
105 { 48000000, P_PLL8, 4, 1, 2 },
106 + { 52000000, P_PLL8, 1, 2, 15 }, /* 51.2 Mhz */
107 { 64000000, P_PLL8, 3, 1, 2 },
108 { 96000000, P_PLL8, 4, 0, 0 },
109 { 192000000, P_PLL8, 2, 0, 0 },
110 @@ -2645,7 +2701,9 @@ static const struct freq_tbl clk_tbl_nss
111 { 110000000, P_PLL18, 1, 1, 5 },
112 { 275000000, P_PLL18, 2, 0, 0 },
113 { 550000000, P_PLL18, 1, 0, 0 },
114 + { 600000000, P_PLL18, 1, 0, 0 },
115 { 733000000, P_PLL18, 1, 0, 0 },
116 + { 800000000, P_PLL18, 1, 0, 0 },
120 @@ -2757,6 +2815,186 @@ static struct clk_dyn_rcg ubi32_core2_sr
124 +static const struct freq_tbl clk_tbl_ce5_core[] = {
125 + { 150000000, P_PLL3, 8, 1, 1 },
126 + { 213200000, P_PLL11, 5, 1, 1 },
130 +static struct clk_dyn_rcg ce5_core_src = {
131 + .ns_reg[0] = 0x36C4,
132 + .ns_reg[1] = 0x36C8,
133 + .bank_reg = 0x36C0,
135 + .src_sel_shift = 0,
136 + .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
139 + .src_sel_shift = 0,
140 + .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
143 + .pre_div_shift = 3,
144 + .pre_div_width = 4,
147 + .pre_div_shift = 3,
148 + .pre_div_width = 4,
151 + .freq_tbl = clk_tbl_ce5_core,
153 + .enable_reg = 0x36C0,
154 + .enable_mask = BIT(1),
155 + .hw.init = &(struct clk_init_data){
156 + .name = "ce5_core_src",
157 + .parent_names = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
159 + .ops = &clk_dyn_rcg_ops,
164 +static struct clk_branch ce5_core_clk = {
165 + .halt_reg = 0x2FDC,
167 + .hwcg_reg = 0x36CC,
170 + .enable_reg = 0x36CC,
171 + .enable_mask = BIT(4),
172 + .hw.init = &(struct clk_init_data){
173 + .name = "ce5_core_clk",
174 + .parent_names = (const char *[]){
178 + .ops = &clk_branch_ops,
179 + .flags = CLK_SET_RATE_PARENT,
184 +static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
185 + { 160000000, P_PLL0, 5, 1, 1 },
186 + { 213200000, P_PLL11, 5, 1, 1 },
190 +static struct clk_dyn_rcg ce5_a_clk_src = {
191 + .ns_reg[0] = 0x3d84,
192 + .ns_reg[1] = 0x3d88,
193 + .bank_reg = 0x3d80,
195 + .src_sel_shift = 0,
196 + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
199 + .src_sel_shift = 0,
200 + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
203 + .pre_div_shift = 3,
204 + .pre_div_width = 4,
207 + .pre_div_shift = 3,
208 + .pre_div_width = 4,
211 + .freq_tbl = clk_tbl_ce5_a_clk,
213 + .enable_reg = 0x3d80,
214 + .enable_mask = BIT(1),
215 + .hw.init = &(struct clk_init_data){
216 + .name = "ce5_a_clk_src",
217 + .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
219 + .ops = &clk_dyn_rcg_ops,
224 +static struct clk_branch ce5_a_clk = {
225 + .halt_reg = 0x3c20,
227 + .hwcg_reg = 0x3d8c,
230 + .enable_reg = 0x3d8c,
231 + .enable_mask = BIT(4),
232 + .hw.init = &(struct clk_init_data){
233 + .name = "ce5_a_clk",
234 + .parent_names = (const char *[]){
238 + .ops = &clk_branch_ops,
239 + .flags = CLK_SET_RATE_PARENT,
244 +static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
245 + { 160000000, P_PLL0, 5, 1, 1 },
246 + { 213200000, P_PLL11, 5, 1, 1 },
250 +static struct clk_dyn_rcg ce5_h_clk_src = {
251 + .ns_reg[0] = 0x3c64,
252 + .ns_reg[1] = 0x3c68,
253 + .bank_reg = 0x3c60,
255 + .src_sel_shift = 0,
256 + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
259 + .src_sel_shift = 0,
260 + .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
263 + .pre_div_shift = 3,
264 + .pre_div_width = 4,
267 + .pre_div_shift = 3,
268 + .pre_div_width = 4,
271 + .freq_tbl = clk_tbl_ce5_h_clk,
273 + .enable_reg = 0x3c60,
274 + .enable_mask = BIT(1),
275 + .hw.init = &(struct clk_init_data){
276 + .name = "ce5_h_clk_src",
277 + .parent_names = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
279 + .ops = &clk_dyn_rcg_ops,
284 +static struct clk_branch ce5_h_clk = {
285 + .halt_reg = 0x3c20,
287 + .hwcg_reg = 0x3c6c,
290 + .enable_reg = 0x3c6c,
291 + .enable_mask = BIT(4),
292 + .hw.init = &(struct clk_init_data){
293 + .name = "ce5_h_clk",
294 + .parent_names = (const char *[]){
298 + .ops = &clk_branch_ops,
299 + .flags = CLK_SET_RATE_PARENT,
304 static struct clk_regmap *gcc_ipq806x_clks[] = {
306 [PLL0_VOTE] = &pll0_vote,
307 @@ -2764,6 +3002,7 @@ static struct clk_regmap *gcc_ipq806x_cl
308 [PLL4_VOTE] = &pll4_vote,
310 [PLL8_VOTE] = &pll8_vote,
311 + [PLL11] = &pll11.clkr,
312 [PLL14] = &pll14.clkr,
313 [PLL14_VOTE] = &pll14_vote,
314 [PLL18] = &pll18.clkr,
315 @@ -2878,6 +3117,12 @@ static struct clk_regmap *gcc_ipq806x_cl
316 [PLL9] = &hfpll0.clkr,
317 [PLL10] = &hfpll1.clkr,
318 [PLL12] = &hfpll_l2.clkr,
319 + [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
320 + [CE5_A_CLK] = &ce5_a_clk.clkr,
321 + [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
322 + [CE5_H_CLK] = &ce5_h_clk.clkr,
323 + [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
324 + [CE5_CORE_CLK] = &ce5_core_clk.clkr,
327 static const struct qcom_reset_map gcc_ipq806x_resets[] = {
328 @@ -3009,6 +3254,11 @@ static const struct qcom_reset_map gcc_i
329 [GMAC_CORE3_RESET] = { 0x3cfc, 0 },
330 [GMAC_CORE4_RESET] = { 0x3d1c, 0 },
331 [GMAC_AHB_RESET] = { 0x3e24, 0 },
332 + [CRYPTO_ENG1_RESET] = { 0x3e00, 0},
333 + [CRYPTO_ENG2_RESET] = { 0x3e04, 0},
334 + [CRYPTO_ENG3_RESET] = { 0x3e08, 0},
335 + [CRYPTO_ENG4_RESET] = { 0x3e0c, 0},
336 + [CRYPTO_AHB_RESET] = { 0x3e10, 0},
337 [NSS_CH0_RST_RX_CLK_N_RESET] = { 0x3b60, 0 },
338 [NSS_CH0_RST_TX_CLK_N_RESET] = { 0x3b60, 1 },
339 [NSS_CH0_RST_RX_125M_N_RESET] = { 0x3b60, 2 },
340 --- a/include/dt-bindings/clock/qcom,gcc-ipq806x.h
341 +++ b/include/dt-bindings/clock/qcom,gcc-ipq806x.h
344 #define PLL14_VOTE 233
347 +#define CE5_A_CLK 235
348 #define CE5_H_CLK 236
349 #define CE5_CORE_CLK 237
350 #define CE3_SLEEP_CLK 238
352 #define EBI2_AON_CLK 281
353 #define NSSTCM_CLK_SRC 282
354 #define NSSTCM_CLK 283
355 +#define CE5_A_CLK_SRC 285
356 +#define CE5_H_CLK_SRC 286
357 +#define CE5_CORE_CLK_SRC 287
360 --- a/include/dt-bindings/reset/qcom,gcc-ipq806x.h
361 +++ b/include/dt-bindings/reset/qcom,gcc-ipq806x.h
363 #define NSS_CAL_PRBS_RST_N_RESET 154
364 #define NSS_LCKDT_RST_N_RESET 155
365 #define NSS_SRDS_N_RESET 156
366 +#define CRYPTO_ENG1_RESET 157
367 +#define CRYPTO_ENG2_RESET 158
368 +#define CRYPTO_ENG3_RESET 159
369 +#define CRYPTO_ENG4_RESET 160
370 +#define CRYPTO_AHB_RESET 161