1 From 72ad7207954dd622a662ba884dc6c30a820123f2 Mon Sep 17 00:00:00 2001
2 From: Stephen Boyd <sboyd@codeaurora.org>
3 Date: Tue, 14 Aug 2018 17:42:24 +0530
4 Subject: [PATCH 05/12] clk: qcom: Add MSM8960/APQ8064's HFPLLs
6 Describe the HFPLLs present on MSM8960 and APQ8064 devices.
8 Acked-by: Rob Herring <robh@kernel.org> (bindings)
9 Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
10 Signed-off-by: Sricharan R <sricharan@codeaurora.org>
11 Tested-by: Craig Tatlor <ctatlor97@gmail.com>
12 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
14 drivers/clk/qcom/gcc-msm8960.c | 172 +++++++++++++++++++
15 include/dt-bindings/clock/qcom,gcc-msm8960.h | 2 +
16 2 files changed, 174 insertions(+)
18 --- a/drivers/clk/qcom/gcc-msm8960.c
19 +++ b/drivers/clk/qcom/gcc-msm8960.c
23 #include "clk-branch.h"
24 +#include "clk-hfpll.h"
27 static struct clk_pll pll3 = {
28 @@ -86,6 +87,164 @@ static struct clk_regmap pll8_vote = {
32 +static struct hfpll_data hfpll0_data = {
37 + .config_reg = 0x3204,
38 + .status_reg = 0x321c,
39 + .config_val = 0x7845c665,
40 + .droop_reg = 0x3214,
41 + .droop_val = 0x0108c000,
42 + .min_rate = 600000000UL,
43 + .max_rate = 1800000000UL,
46 +static struct clk_hfpll hfpll0 = {
48 + .clkr.hw.init = &(struct clk_init_data){
49 + .parent_names = (const char *[]){ "pxo" },
52 + .ops = &clk_ops_hfpll,
53 + .flags = CLK_IGNORE_UNUSED,
55 + .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
58 +static struct hfpll_data hfpll1_8064_data = {
63 + .config_reg = 0x3244,
64 + .status_reg = 0x325c,
65 + .config_val = 0x7845c665,
66 + .droop_reg = 0x3254,
67 + .droop_val = 0x0108c000,
68 + .min_rate = 600000000UL,
69 + .max_rate = 1800000000UL,
72 +static struct hfpll_data hfpll1_data = {
77 + .config_reg = 0x3304,
78 + .status_reg = 0x331c,
79 + .config_val = 0x7845c665,
80 + .droop_reg = 0x3314,
81 + .droop_val = 0x0108c000,
82 + .min_rate = 600000000UL,
83 + .max_rate = 1800000000UL,
86 +static struct clk_hfpll hfpll1 = {
88 + .clkr.hw.init = &(struct clk_init_data){
89 + .parent_names = (const char *[]){ "pxo" },
92 + .ops = &clk_ops_hfpll,
93 + .flags = CLK_IGNORE_UNUSED,
95 + .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
98 +static struct hfpll_data hfpll2_data = {
103 + .config_reg = 0x3284,
104 + .status_reg = 0x329c,
105 + .config_val = 0x7845c665,
106 + .droop_reg = 0x3294,
107 + .droop_val = 0x0108c000,
108 + .min_rate = 600000000UL,
109 + .max_rate = 1800000000UL,
112 +static struct clk_hfpll hfpll2 = {
114 + .clkr.hw.init = &(struct clk_init_data){
115 + .parent_names = (const char *[]){ "pxo" },
118 + .ops = &clk_ops_hfpll,
119 + .flags = CLK_IGNORE_UNUSED,
121 + .lock = __SPIN_LOCK_UNLOCKED(hfpll2.lock),
124 +static struct hfpll_data hfpll3_data = {
125 + .mode_reg = 0x32c0,
129 + .config_reg = 0x32c4,
130 + .status_reg = 0x32dc,
131 + .config_val = 0x7845c665,
132 + .droop_reg = 0x32d4,
133 + .droop_val = 0x0108c000,
134 + .min_rate = 600000000UL,
135 + .max_rate = 1800000000UL,
138 +static struct clk_hfpll hfpll3 = {
140 + .clkr.hw.init = &(struct clk_init_data){
141 + .parent_names = (const char *[]){ "pxo" },
144 + .ops = &clk_ops_hfpll,
145 + .flags = CLK_IGNORE_UNUSED,
147 + .lock = __SPIN_LOCK_UNLOCKED(hfpll3.lock),
150 +static struct hfpll_data hfpll_l2_8064_data = {
151 + .mode_reg = 0x3300,
155 + .config_reg = 0x3304,
156 + .status_reg = 0x331c,
157 + .config_val = 0x7845c665,
158 + .droop_reg = 0x3314,
159 + .droop_val = 0x0108c000,
160 + .min_rate = 600000000UL,
161 + .max_rate = 1800000000UL,
164 +static struct hfpll_data hfpll_l2_data = {
165 + .mode_reg = 0x3400,
169 + .config_reg = 0x3404,
170 + .status_reg = 0x341c,
171 + .config_val = 0x7845c665,
172 + .droop_reg = 0x3414,
173 + .droop_val = 0x0108c000,
174 + .min_rate = 600000000UL,
175 + .max_rate = 1800000000UL,
178 +static struct clk_hfpll hfpll_l2 = {
179 + .d = &hfpll_l2_data,
180 + .clkr.hw.init = &(struct clk_init_data){
181 + .parent_names = (const char *[]){ "pxo" },
183 + .name = "hfpll_l2",
184 + .ops = &clk_ops_hfpll,
185 + .flags = CLK_IGNORE_UNUSED,
187 + .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
190 static struct clk_pll pll14 = {
193 @@ -3107,6 +3266,9 @@ static struct clk_regmap *gcc_msm8960_cl
194 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
195 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
196 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
197 + [PLL9] = &hfpll0.clkr,
198 + [PLL10] = &hfpll1.clkr,
199 + [PLL12] = &hfpll_l2.clkr,
202 static const struct qcom_reset_map gcc_msm8960_resets[] = {
203 @@ -3318,6 +3480,11 @@ static struct clk_regmap *gcc_apq8064_cl
204 [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
205 [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
206 [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
207 + [PLL9] = &hfpll0.clkr,
208 + [PLL10] = &hfpll1.clkr,
209 + [PLL12] = &hfpll_l2.clkr,
210 + [PLL16] = &hfpll2.clkr,
211 + [PLL17] = &hfpll3.clkr,
214 static const struct qcom_reset_map gcc_apq8064_resets[] = {
215 @@ -3477,6 +3644,11 @@ static int gcc_msm8960_probe(struct plat
219 + if (match->data == &gcc_apq8064_desc) {
220 + hfpll1.d = &hfpll1_8064_data;
221 + hfpll_l2.d = &hfpll_l2_8064_data;
224 tsens = platform_device_register_data(&pdev->dev, "qcom-tsens", -1,
227 --- a/include/dt-bindings/clock/qcom,gcc-msm8960.h
228 +++ b/include/dt-bindings/clock/qcom,gcc-msm8960.h
231 #define CE3_CORE_CLK 304
232 #define CE3_H_CLK 305