1 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
2 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
4 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/soc/qcom,gsbi.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 +#include <dt-bindings/mfd/qcom-rpm.h>
8 +#include <dt-bindings/clock/qcom,rpmcc.h>
13 next-level-cache = <&L2>;
16 + clocks = <&kraitcc 0>, <&kraitcc 4>;
17 + clock-names = "cpu", "l2";
18 + clock-latency = <100000>;
19 + cpu-supply = <&smb208_s2a>;
20 + operating-points-v2 = <&opp_table0>;
21 + voltage-tolerance = <5>;
22 + cooling-min-state = <0>;
23 + cooling-max-state = <10>;
24 + #cooling-cells = <2>;
25 + cpu-idle-states = <&CPU_SPC>;
30 next-level-cache = <&L2>;
33 + clocks = <&kraitcc 1>, <&kraitcc 4>;
34 + clock-names = "cpu", "l2";
35 + clock-latency = <100000>;
36 + cpu-supply = <&smb208_s2b>;
37 + operating-points-v2 = <&opp_table0>;
38 + voltage-tolerance = <5>;
39 + cooling-min-state = <0>;
40 + cooling-max-state = <10>;
41 + #cooling-cells = <2>;
42 + cpu-idle-states = <&CPU_SPC>;
46 - compatible = "cache";
50 + compatible = "qcom,idle-state-spc", "arm,idle-state";
51 + status = "disabled";
52 + entry-latency-us = <400>;
53 + exit-latency-us = <900>;
54 + min-residency-us = <3000>;
59 + opp_table_l2: opp_table_l2 {
60 + compatible = "operating-points-v2";
63 + opp-hz = /bits/ 64 <384000000>;
64 + opp-microvolt = <1100000>;
65 + clock-latency-ns = <100000>;
70 + opp-hz = /bits/ 64 <1000000000>;
71 + opp-microvolt = <1100000>;
72 + clock-latency-ns = <100000>;
77 + opp-hz = /bits/ 64 <1200000000>;
78 + opp-microvolt = <1150000>;
79 + clock-latency-ns = <100000>;
84 + opp_table0: opp_table0 {
85 + compatible = "operating-points-v2-kryo-cpu";
86 + nvmem-cells = <&speedbin_efuse>;
89 + opp-hz = /bits/ 64 <384000000>;
90 + opp-microvolt-speed0-pvs0-v0 = <1000000>;
91 + opp-microvolt-speed0-pvs1-v0 = <925000>;
92 + opp-microvolt-speed0-pvs2-v0 = <875000>;
93 + opp-microvolt-speed0-pvs3-v0 = <800000>;
94 + opp-supported-hw = <0x1>;
95 + clock-latency-ns = <100000>;
100 + opp-hz = /bits/ 64 <600000000>;
101 + opp-microvolt-speed0-pvs0-v0 = <1050000>;
102 + opp-microvolt-speed0-pvs1-v0 = <975000>;
103 + opp-microvolt-speed0-pvs2-v0 = <925000>;
104 + opp-microvolt-speed0-pvs3-v0 = <850000>;
105 + opp-supported-hw = <0x1>;
106 + clock-latency-ns = <100000>;
111 + opp-hz = /bits/ 64 <800000000>;
112 + opp-microvolt-speed0-pvs0-v0 = <1100000>;
113 + opp-microvolt-speed0-pvs1-v0 = <1025000>;
114 + opp-microvolt-speed0-pvs2-v0 = <995000>;
115 + opp-microvolt-speed0-pvs3-v0 = <900000>;
116 + opp-supported-hw = <0x1>;
117 + clock-latency-ns = <100000>;
122 + opp-hz = /bits/ 64 <1000000000>;
123 + opp-microvolt-speed0-pvs0-v0 = <1150000>;
124 + opp-microvolt-speed0-pvs1-v0 = <1075000>;
125 + opp-microvolt-speed0-pvs2-v0 = <1025000>;
126 + opp-microvolt-speed0-pvs3-v0 = <950000>;
127 + opp-supported-hw = <0x1>;
128 + clock-latency-ns = <100000>;
133 + opp-hz = /bits/ 64 <1200000000>;
134 + opp-microvolt-speed0-pvs0-v0 = <1200000>;
135 + opp-microvolt-speed0-pvs1-v0 = <1125000>;
136 + opp-microvolt-speed0-pvs2-v0 = <1075000>;
137 + opp-microvolt-speed0-pvs3-v0 = <1000000>;
138 + opp-supported-hw = <0x1>;
139 + clock-latency-ns = <100000>;
144 + opp-hz = /bits/ 64 <1400000000>;
145 + opp-microvolt-speed0-pvs0-v0 = <1250000>;
146 + opp-microvolt-speed0-pvs1-v0 = <1175000>;
147 + opp-microvolt-speed0-pvs2-v0 = <1125000>;
148 + opp-microvolt-speed0-pvs3-v0 = <1050000>;
149 + opp-supported-hw = <0x1>;
150 + clock-latency-ns = <100000>;
157 + polling-delay-passive = <0>;
158 + polling-delay = <0>;
159 + thermal-sensors = <&tsens 0>;
163 + temperature = <125000>;
164 + hysteresis = <2000>;
165 + type = "critical_high";
169 + temperature = <105000>;
170 + hysteresis = <2000>;
171 + type = "configurable_hi";
175 + temperature = <95000>;
176 + hysteresis = <2000>;
177 + type = "configurable_lo";
182 + hysteresis = <2000>;
183 + type = "critical_low";
189 + polling-delay-passive = <0>;
190 + polling-delay = <0>;
191 + thermal-sensors = <&tsens 1>;
195 + temperature = <125000>;
196 + hysteresis = <2000>;
197 + type = "critical_high";
201 + temperature = <105000>;
202 + hysteresis = <2000>;
203 + type = "configurable_hi";
207 + temperature = <95000>;
208 + hysteresis = <2000>;
209 + type = "configurable_lo";
214 + hysteresis = <2000>;
215 + type = "critical_low";
221 + polling-delay-passive = <0>;
222 + polling-delay = <0>;
223 + thermal-sensors = <&tsens 2>;
227 + temperature = <125000>;
228 + hysteresis = <2000>;
229 + type = "critical_high";
233 + temperature = <105000>;
234 + hysteresis = <2000>;
235 + type = "configurable_hi";
239 + temperature = <95000>;
240 + hysteresis = <2000>;
241 + type = "configurable_lo";
246 + hysteresis = <2000>;
247 + type = "critical_low";
253 + polling-delay-passive = <0>;
254 + polling-delay = <0>;
255 + thermal-sensors = <&tsens 3>;
259 + temperature = <125000>;
260 + hysteresis = <2000>;
261 + type = "critical_high";
265 + temperature = <105000>;
266 + hysteresis = <2000>;
267 + type = "configurable_hi";
271 + temperature = <95000>;
272 + hysteresis = <2000>;
273 + type = "configurable_lo";
278 + hysteresis = <2000>;
279 + type = "critical_low";
285 + polling-delay-passive = <0>;
286 + polling-delay = <0>;
287 + thermal-sensors = <&tsens 4>;
291 + temperature = <125000>;
292 + hysteresis = <2000>;
293 + type = "critical_high";
297 + temperature = <105000>;
298 + hysteresis = <2000>;
299 + type = "configurable_hi";
303 + temperature = <95000>;
304 + hysteresis = <2000>;
305 + type = "configurable_lo";
310 + hysteresis = <2000>;
311 + type = "critical_low";
317 + polling-delay-passive = <0>;
318 + polling-delay = <0>;
319 + thermal-sensors = <&tsens 5>;
323 + temperature = <125000>;
324 + hysteresis = <2000>;
325 + type = "critical_high";
329 + temperature = <105000>;
330 + hysteresis = <2000>;
331 + type = "configurable_hi";
335 + temperature = <95000>;
336 + hysteresis = <2000>;
337 + type = "configurable_lo";
342 + hysteresis = <2000>;
343 + type = "critical_low";
349 + polling-delay-passive = <0>;
350 + polling-delay = <0>;
351 + thermal-sensors = <&tsens 6>;
355 + temperature = <125000>;
356 + hysteresis = <2000>;
357 + type = "critical_high";
361 + temperature = <105000>;
362 + hysteresis = <2000>;
363 + type = "configurable_hi";
367 + temperature = <95000>;
368 + hysteresis = <2000>;
369 + type = "configurable_lo";
374 + hysteresis = <2000>;
375 + type = "critical_low";
381 + polling-delay-passive = <0>;
382 + polling-delay = <0>;
383 + thermal-sensors = <&tsens 7>;
387 + temperature = <125000>;
388 + hysteresis = <2000>;
389 + type = "critical_high";
393 + temperature = <105000>;
394 + hysteresis = <2000>;
395 + type = "configurable_hi";
399 + temperature = <95000>;
400 + hysteresis = <2000>;
401 + type = "configurable_lo";
406 + hysteresis = <2000>;
407 + type = "critical_low";
413 + polling-delay-passive = <0>;
414 + polling-delay = <0>;
415 + thermal-sensors = <&tsens 8>;
419 + temperature = <125000>;
420 + hysteresis = <2000>;
421 + type = "critical_high";
425 + temperature = <105000>;
426 + hysteresis = <2000>;
427 + type = "configurable_hi";
431 + temperature = <95000>;
432 + hysteresis = <2000>;
433 + type = "configurable_lo";
438 + hysteresis = <2000>;
439 + type = "critical_low";
445 + polling-delay-passive = <0>;
446 + polling-delay = <0>;
447 + thermal-sensors = <&tsens 9>;
451 + temperature = <125000>;
452 + hysteresis = <2000>;
453 + type = "critical_high";
457 + temperature = <105000>;
458 + hysteresis = <2000>;
459 + type = "configurable_hi";
463 + temperature = <95000>;
464 + hysteresis = <2000>;
465 + type = "configurable_lo";
470 + hysteresis = <2000>;
471 + type = "critical_low";
476 + tsens_tz_sensor10 {
477 + polling-delay-passive = <0>;
478 + polling-delay = <0>;
479 + thermal-sensors = <&tsens 10>;
483 + temperature = <125000>;
484 + hysteresis = <2000>;
485 + type = "critical_high";
489 + temperature = <105000>;
490 + hysteresis = <2000>;
491 + type = "configurable_hi";
495 + temperature = <95000>;
496 + hysteresis = <2000>;
497 + type = "configurable_lo";
502 + hysteresis = <2000>;
503 + type = "critical_low";
514 + compatible = "qcom,fab-scaling";
515 + clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
516 + clock-names = "apps-fab-clk", "ddr-fab-clk";
517 + fab_freq_high = <533000000>;
518 + fab_freq_nominal = <400000000>;
519 + cpu_freq_threshold = <1000000000>;
524 compatible = "qcom,scm-ipq806x", "qcom,scm";
526 reg-names = "lpass-lpaif";
530 + compatible = "qcom,krait-cache", "cache";
532 + qcom,saw = <&saw_l2>;
534 + clocks = <&kraitcc 4>;
535 + clock-names = "l2";
536 + l2-supply = <&smb208_s1a>;
537 + operating-points-v2 = <&opp_table_l2>;
540 + qfprom: qfprom@700000 {
541 + compatible = "qcom,qfprom", "syscon";
542 + reg = <0x700000 0x1000>;
543 + #address-cells = <1>;
546 + tsens_calib: calib@400 {
549 + tsens_backup: backup@410 {
552 + speedbin_efuse: speedbin@0c0 {
558 + compatible = "qcom,rpm-ipq8064";
559 + reg = <0x108000 0x1000>;
560 + qcom,ipc = <&l2cc 0x8 2>;
562 + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
563 + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
564 + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
565 + interrupt-names = "ack", "err", "wakeup";
567 + clocks = <&gcc RPM_MSG_RAM_H_CLK>;
568 + clock-names = "ram";
570 + #address-cells = <1>;
573 + rpmcc: clock-controller {
574 + compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
575 + #clock-cells = <1>;
579 + compatible = "qcom,rpm-smb208-regulators";
582 + regulator-min-microvolt = <1050000>;
583 + regulator-max-microvolt = <1150000>;
585 + qcom,switch-mode-frequency = <1200000>;
589 + regulator-min-microvolt = <1050000>;
590 + regulator-max-microvolt = <1150000>;
592 + qcom,switch-mode-frequency = <1200000>;
596 + regulator-min-microvolt = < 800000>;
597 + regulator-max-microvolt = <1250000>;
599 + qcom,switch-mode-frequency = <1200000>;
603 + regulator-min-microvolt = < 800000>;
604 + regulator-max-microvolt = <1250000>;
606 + qcom,switch-mode-frequency = <1200000>;
612 + compatible = "qcom,prng";
613 + reg = <0x1a500000 0x200>;
614 + clocks = <&gcc PRNG_CLK>;
615 + clock-names = "core";
618 qcom_pinmux: pinmux@800000 {
619 compatible = "qcom,ipq8064-pinctrl";
620 reg = <0x800000 0x4000>;
625 + i2c4_pins: i2c4_pinmux {
627 + pins = "gpio12", "gpio13";
628 + function = "gsbi4";
629 + drive-strength = <12>;
636 pins = "gpio18", "gpio19", "gpio21";
641 + nand_pins: nand_pins {
643 + pins = "gpio34", "gpio35", "gpio36",
644 + "gpio37", "gpio38";
646 + drive-strength = <10>;
653 + drive-strength = <10>;
658 + pins = "gpio40", "gpio41", "gpio42",
659 + "gpio43", "gpio44", "gpio45",
660 + "gpio46", "gpio47";
662 + drive-strength = <10>;
667 + mdio0_pins: mdio0_pins {
669 + pins = "gpio0", "gpio1";
671 + drive-strength = <8>;
676 + rgmii2_pins: rgmii2_pins {
678 + pins = "gpio27", "gpio28", "gpio29",
679 + "gpio30", "gpio31", "gpio32",
680 + "gpio51", "gpio52", "gpio59",
681 + "gpio60", "gpio61", "gpio62";
682 + function = "rgmii2";
683 + drive-strength = <8>;
688 leds_pins: leds_pins {
690 pins = "gpio7", "gpio8", "gpio9",
692 clock-output-names = "acpu1_aux";
695 + l2cc: clock-controller@2011000 {
696 + compatible = "qcom,kpss-gcc", "syscon";
697 + reg = <0x2011000 0x1000>;
698 + clock-output-names = "acpu_l2_aux";
701 + kraitcc: clock-controller {
702 + compatible = "qcom,krait-cc-v1";
703 + #clock-cells = <1>;
706 saw0: regulator@2089000 {
707 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
708 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
713 + saw_l2: regulator@02012000 {
714 + compatible = "qcom,saw2", "syscon";
715 + reg = <0x02012000 0x1000>;
719 + sic_non_secure: sic-non-secure@12100000 {
720 + compatible = "syscon";
721 + reg = <0x12100000 0x10000>;
724 gsbi2: gsbi@12480000 {
725 compatible = "qcom,gsbi-v1.0.0";
727 @@ -436,6 +1089,15 @@
728 #power-domain-cells = <1>;
731 + tsens: thermal-sensor@900000 {
732 + compatible = "qcom,ipq8064-tsens";
733 + reg = <0x900000 0x3680>;
734 + nvmem-cells = <&tsens_calib>, <&tsens_backup>;
735 + nvmem-cell-names = "calib", "calib_backup";
736 + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
737 + #thermal-sensor-cells = <1>;
740 tcsr: syscon@1a400000 {
741 compatible = "qcom,tcsr-ipq8064", "syscon";
742 reg = <0x1a400000 0x100>;
743 @@ -448,6 +1110,95 @@
747 + sfpb_mutex_block: syscon@1200600 {
748 + compatible = "syscon";
749 + reg = <0x01200600 0x100>;
752 + hs_phy_0: hs_phy_0 {
753 + compatible = "qcom,ipq806x-usb-phy-hs";
754 + reg = <0x110f8800 0x30>;
755 + clocks = <&gcc USB30_0_UTMI_CLK>;
756 + clock-names = "ref";
760 + ss_phy_0: ss_phy_0 {
761 + compatible = "qcom,ipq806x-usb-phy-ss";
762 + reg = <0x110f8830 0x30>;
763 + clocks = <&gcc USB30_0_MASTER_CLK>;
764 + clock-names = "ref";
768 + usb3_0: usb3@110f8800 {
769 + compatible = "qcom,dwc3", "syscon";
770 + #address-cells = <1>;
772 + reg = <0x110f8800 0x8000>;
773 + clocks = <&gcc USB30_0_MASTER_CLK>;
774 + clock-names = "core";
778 + resets = <&gcc USB30_0_MASTER_RESET>;
779 + reset-names = "master";
781 + status = "disabled";
783 + dwc3_0: dwc3@11000000 {
784 + compatible = "snps,dwc3";
785 + reg = <0x11000000 0xcd00>;
786 + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
787 + phys = <&hs_phy_0>, <&ss_phy_0>;
788 + phy-names = "usb2-phy", "usb3-phy";
790 + snps,dis_u3_susphy_quirk;
794 + hs_phy_1: hs_phy_1 {
795 + compatible = "qcom,ipq806x-usb-phy-hs";
796 + reg = <0x100f8800 0x30>;
797 + clocks = <&gcc USB30_1_UTMI_CLK>;
798 + clock-names = "ref";
802 + ss_phy_1: ss_phy_1 {
803 + compatible = "qcom,ipq806x-usb-phy-ss";
804 + reg = <0x100f8830 0x30>;
805 + clocks = <&gcc USB30_1_MASTER_CLK>;
806 + clock-names = "ref";
810 + usb3_1: usb3@100f8800 {
811 + compatible = "qcom,dwc3", "syscon";
812 + #address-cells = <1>;
814 + reg = <0x100f8800 0x8000>;
815 + clocks = <&gcc USB30_1_MASTER_CLK>;
816 + clock-names = "core";
820 + resets = <&gcc USB30_1_MASTER_RESET>;
821 + reset-names = "master";
823 + status = "disabled";
825 + dwc3_1: dwc3@10000000 {
826 + compatible = "snps,dwc3";
827 + reg = <0x10000000 0xcd00>;
828 + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
829 + phys = <&hs_phy_1>, <&ss_phy_1>;
830 + phy-names = "usb2-phy", "usb3-phy";
832 + snps,dis_u3_susphy_quirk;
836 pcie0: pci@1b500000 {
837 compatible = "qcom,pcie-ipq8064";
838 reg = <0x1b500000 0x1000
839 @@ -601,6 +1352,167 @@
840 perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
843 + adm_dma: dma@18300000 {
844 + compatible = "qcom,adm";
845 + reg = <0x18300000 0x100000>;
846 + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
849 + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
850 + clock-names = "core", "iface";
852 + resets = <&gcc ADM0_RESET>,
853 + <&gcc ADM0_PBUS_RESET>,
854 + <&gcc ADM0_C0_RESET>,
855 + <&gcc ADM0_C1_RESET>,
856 + <&gcc ADM0_C2_RESET>;
857 + reset-names = "clk", "pbus", "c0", "c1", "c2";
860 + status = "disabled";
863 + nand_controller: nand-controller@1ac00000 {
864 + compatible = "qcom,ipq806x-nand";
865 + reg = <0x1ac00000 0x800>;
867 + clocks = <&gcc EBI2_CLK>,
868 + <&gcc EBI2_AON_CLK>;
869 + clock-names = "core", "aon";
871 + dmas = <&adm_dma 3>;
872 + dma-names = "rxtx";
873 + qcom,cmd-crci = <15>;
874 + qcom,data-crci = <3>;
876 + status = "disabled";
878 + #address-cells = <1>;
882 + nss_common: syscon@03000000 {
883 + compatible = "syscon";
884 + reg = <0x03000000 0x0000FFFF>;
887 + qsgmii_csr: syscon@1bb00000 {
888 + compatible = "syscon";
889 + reg = <0x1bb00000 0x000001FF>;
892 + stmmac_axi_setup: stmmac-axi-config {
893 + snps,wr_osr_lmt = <7>;
894 + snps,rd_osr_lmt = <7>;
895 + snps,blen = <16 0 0 0 0 0 0>;
898 + mdio0: mdio@37000000 {
899 + #address-cells = <1>;
902 + compatible = "qcom,ipq8064-mdio", "syscon";
903 + reg = <0x37000000 0x200000>;
904 + resets = <&gcc GMAC_CORE1_RESET>;
905 + reset-names = "stmmaceth";
906 + clocks = <&gcc GMAC_CORE1_CLK>;
907 + clock-names = "stmmaceth";
909 + status = "disabled";
912 + gmac0: ethernet@37000000 {
913 + device_type = "network";
914 + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
915 + reg = <0x37000000 0x200000>;
916 + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
917 + interrupt-names = "macirq";
919 + snps,axi-config = <&stmmac_axi_setup>;
923 + qcom,nss-common = <&nss_common>;
924 + qcom,qsgmii-csr = <&qsgmii_csr>;
926 + clocks = <&gcc GMAC_CORE1_CLK>;
927 + clock-names = "stmmaceth";
929 + resets = <&gcc GMAC_CORE1_RESET>;
930 + reset-names = "stmmaceth";
932 + status = "disabled";
935 + gmac1: ethernet@37200000 {
936 + device_type = "network";
937 + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
938 + reg = <0x37200000 0x200000>;
939 + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
940 + interrupt-names = "macirq";
942 + snps,axi-config = <&stmmac_axi_setup>;
946 + qcom,nss-common = <&nss_common>;
947 + qcom,qsgmii-csr = <&qsgmii_csr>;
949 + clocks = <&gcc GMAC_CORE2_CLK>;
950 + clock-names = "stmmaceth";
952 + resets = <&gcc GMAC_CORE2_RESET>;
953 + reset-names = "stmmaceth";
955 + status = "disabled";
958 + gmac2: ethernet@37400000 {
959 + device_type = "network";
960 + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
961 + reg = <0x37400000 0x200000>;
962 + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
963 + interrupt-names = "macirq";
965 + snps,axi-config = <&stmmac_axi_setup>;
969 + qcom,nss-common = <&nss_common>;
970 + qcom,qsgmii-csr = <&qsgmii_csr>;
972 + clocks = <&gcc GMAC_CORE3_CLK>;
973 + clock-names = "stmmaceth";
975 + resets = <&gcc GMAC_CORE3_RESET>;
976 + reset-names = "stmmaceth";
978 + status = "disabled";
981 + gmac3: ethernet@37600000 {
982 + device_type = "network";
983 + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
984 + reg = <0x37600000 0x200000>;
985 + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
986 + interrupt-names = "macirq";
988 + snps,axi-config = <&stmmac_axi_setup>;
992 + qcom,nss-common = <&nss_common>;
993 + qcom,qsgmii-csr = <&qsgmii_csr>;
995 + clocks = <&gcc GMAC_CORE4_CLK>;
996 + clock-names = "stmmaceth";
998 + resets = <&gcc GMAC_CORE4_RESET>;
999 + reset-names = "stmmaceth";
1001 + status = "disabled";
1004 vsdcc_fixed: vsdcc-regulator {
1005 compatible = "regulator-fixed";
1006 regulator-name = "SDCC Power";
1007 @@ -676,4 +1588,17 @@
1012 + sfpb_mutex: sfpb-mutex {
1013 + compatible = "qcom,sfpb-mutex";
1014 + syscon = <&sfpb_mutex_block 4 4>;
1016 + #hwlock-cells = <1>;
1020 + compatible = "qcom,smem";
1021 + memory-region = <&smem>;
1022 + hwlocks = <&sfpb_mutex 3>;