1 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
2 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
4 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/soc/qcom,gsbi.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 +#include <dt-bindings/mfd/qcom-rpm.h>
8 +#include <dt-bindings/clock/qcom,rpmcc.h>
13 next-level-cache = <&L2>;
16 + clocks = <&kraitcc 0>, <&kraitcc 4>;
17 + clock-names = "cpu", "l2";
18 + clock-latency = <100000>;
19 + cpu-supply = <&smb208_s2a>;
20 + operating-points-v2 = <&opp_table0>;
21 + voltage-tolerance = <5>;
22 + cooling-min-state = <0>;
23 + cooling-max-state = <10>;
24 + #cooling-cells = <2>;
25 + cpu-idle-states = <&CPU_SPC>;
30 next-level-cache = <&L2>;
33 + clocks = <&kraitcc 1>, <&kraitcc 4>;
34 + clock-names = "cpu", "l2";
35 + clock-latency = <100000>;
36 + cpu-supply = <&smb208_s2b>;
37 + operating-points-v2 = <&opp_table0>;
38 + voltage-tolerance = <5>;
39 + cooling-min-state = <0>;
40 + cooling-max-state = <10>;
41 + #cooling-cells = <2>;
42 + cpu-idle-states = <&CPU_SPC>;
48 + qcom,saw = <&saw_l2>;
52 + qcom,l2-rates = <384000000 1000000000 1200000000>;
53 + qcom,l2-cpufreq = <384000000 600000000 1200000000>;
54 + qcom,l2-volt = <1100000 1100000 1150000>;
55 + qcom,l2-supply = <&smb208_s1a>;
60 + compatible = "qcom,idle-state-spc", "arm,idle-state";
61 + status = "disabled";
62 + entry-latency-us = <400>;
63 + exit-latency-us = <900>;
64 + min-residency-us = <3000>;
69 + opp_table0: opp_table0 {
70 + compatible = "operating-points-v2-kryo-cpu";
71 + nvmem-cells = <&speedbin_efuse>;
74 + opp-hz = /bits/ 64 <384000000>;
75 + opp-microvolt-speed0-pvs0-v0 = <1000000>;
76 + opp-microvolt-speed0-pvs1-v0 = <925000>;
77 + opp-microvolt-speed0-pvs2-v0 = <875000>;
78 + opp-microvolt-speed0-pvs3-v0 = <800000>;
79 + opp-supported-hw = <0x1>;
80 + clock-latency-ns = <100000>;
84 + opp-hz = /bits/ 64 <600000000>;
85 + opp-microvolt-speed0-pvs0-v0 = <1050000>;
86 + opp-microvolt-speed0-pvs1-v0 = <975000>;
87 + opp-microvolt-speed0-pvs2-v0 = <925000>;
88 + opp-microvolt-speed0-pvs3-v0 = <850000>;
89 + opp-supported-hw = <0x1>;
90 + clock-latency-ns = <100000>;
94 + opp-hz = /bits/ 64 <800000000>;
95 + opp-microvolt-speed0-pvs0-v0 = <1100000>;
96 + opp-microvolt-speed0-pvs1-v0 = <1025000>;
97 + opp-microvolt-speed0-pvs2-v0 = <995000>;
98 + opp-microvolt-speed0-pvs3-v0 = <900000>;
99 + opp-supported-hw = <0x1>;
100 + clock-latency-ns = <100000>;
104 + opp-hz = /bits/ 64 <1000000000>;
105 + opp-microvolt-speed0-pvs0-v0 = <1150000>;
106 + opp-microvolt-speed0-pvs1-v0 = <1075000>;
107 + opp-microvolt-speed0-pvs2-v0 = <1025000>;
108 + opp-microvolt-speed0-pvs3-v0 = <950000>;
109 + opp-supported-hw = <0x1>;
110 + clock-latency-ns = <100000>;
114 + opp-hz = /bits/ 64 <1200000000>;
115 + opp-microvolt-speed0-pvs0-v0 = <1200000>;
116 + opp-microvolt-speed0-pvs1-v0 = <1125000>;
117 + opp-microvolt-speed0-pvs2-v0 = <1075000>;
118 + opp-microvolt-speed0-pvs3-v0 = <1000000>;
119 + opp-supported-hw = <0x1>;
120 + clock-latency-ns = <100000>;
124 + opp-hz = /bits/ 64 <1400000000>;
125 + opp-microvolt-speed0-pvs0-v0 = <1250000>;
126 + opp-microvolt-speed0-pvs1-v0 = <1175000>;
127 + opp-microvolt-speed0-pvs2-v0 = <1125000>;
128 + opp-microvolt-speed0-pvs3-v0 = <1050000>;
129 + opp-supported-hw = <0x1>;
130 + clock-latency-ns = <100000>;
136 + polling-delay-passive = <0>;
137 + polling-delay = <0>;
138 + thermal-sensors = <&tsens 0>;
142 + temperature = <125000>;
143 + hysteresis = <2000>;
144 + type = "critical_high";
148 + temperature = <105000>;
149 + hysteresis = <2000>;
150 + type = "configurable_hi";
154 + temperature = <95000>;
155 + hysteresis = <2000>;
156 + type = "configurable_lo";
161 + hysteresis = <2000>;
162 + type = "critical_low";
168 + polling-delay-passive = <0>;
169 + polling-delay = <0>;
170 + thermal-sensors = <&tsens 1>;
174 + temperature = <125000>;
175 + hysteresis = <2000>;
176 + type = "critical_high";
180 + temperature = <105000>;
181 + hysteresis = <2000>;
182 + type = "configurable_hi";
186 + temperature = <95000>;
187 + hysteresis = <2000>;
188 + type = "configurable_lo";
193 + hysteresis = <2000>;
194 + type = "critical_low";
200 + polling-delay-passive = <0>;
201 + polling-delay = <0>;
202 + thermal-sensors = <&tsens 2>;
206 + temperature = <125000>;
207 + hysteresis = <2000>;
208 + type = "critical_high";
212 + temperature = <105000>;
213 + hysteresis = <2000>;
214 + type = "configurable_hi";
218 + temperature = <95000>;
219 + hysteresis = <2000>;
220 + type = "configurable_lo";
225 + hysteresis = <2000>;
226 + type = "critical_low";
232 + polling-delay-passive = <0>;
233 + polling-delay = <0>;
234 + thermal-sensors = <&tsens 3>;
238 + temperature = <125000>;
239 + hysteresis = <2000>;
240 + type = "critical_high";
244 + temperature = <105000>;
245 + hysteresis = <2000>;
246 + type = "configurable_hi";
250 + temperature = <95000>;
251 + hysteresis = <2000>;
252 + type = "configurable_lo";
257 + hysteresis = <2000>;
258 + type = "critical_low";
264 + polling-delay-passive = <0>;
265 + polling-delay = <0>;
266 + thermal-sensors = <&tsens 4>;
270 + temperature = <125000>;
271 + hysteresis = <2000>;
272 + type = "critical_high";
276 + temperature = <105000>;
277 + hysteresis = <2000>;
278 + type = "configurable_hi";
282 + temperature = <95000>;
283 + hysteresis = <2000>;
284 + type = "configurable_lo";
289 + hysteresis = <2000>;
290 + type = "critical_low";
296 + polling-delay-passive = <0>;
297 + polling-delay = <0>;
298 + thermal-sensors = <&tsens 5>;
302 + temperature = <125000>;
303 + hysteresis = <2000>;
304 + type = "critical_high";
308 + temperature = <105000>;
309 + hysteresis = <2000>;
310 + type = "configurable_hi";
314 + temperature = <95000>;
315 + hysteresis = <2000>;
316 + type = "configurable_lo";
321 + hysteresis = <2000>;
322 + type = "critical_low";
328 + polling-delay-passive = <0>;
329 + polling-delay = <0>;
330 + thermal-sensors = <&tsens 6>;
334 + temperature = <125000>;
335 + hysteresis = <2000>;
336 + type = "critical_high";
340 + temperature = <105000>;
341 + hysteresis = <2000>;
342 + type = "configurable_hi";
346 + temperature = <95000>;
347 + hysteresis = <2000>;
348 + type = "configurable_lo";
353 + hysteresis = <2000>;
354 + type = "critical_low";
360 + polling-delay-passive = <0>;
361 + polling-delay = <0>;
362 + thermal-sensors = <&tsens 7>;
366 + temperature = <125000>;
367 + hysteresis = <2000>;
368 + type = "critical_high";
372 + temperature = <105000>;
373 + hysteresis = <2000>;
374 + type = "configurable_hi";
378 + temperature = <95000>;
379 + hysteresis = <2000>;
380 + type = "configurable_lo";
385 + hysteresis = <2000>;
386 + type = "critical_low";
392 + polling-delay-passive = <0>;
393 + polling-delay = <0>;
394 + thermal-sensors = <&tsens 8>;
398 + temperature = <125000>;
399 + hysteresis = <2000>;
400 + type = "critical_high";
404 + temperature = <105000>;
405 + hysteresis = <2000>;
406 + type = "configurable_hi";
410 + temperature = <95000>;
411 + hysteresis = <2000>;
412 + type = "configurable_lo";
417 + hysteresis = <2000>;
418 + type = "critical_low";
424 + polling-delay-passive = <0>;
425 + polling-delay = <0>;
426 + thermal-sensors = <&tsens 9>;
430 + temperature = <125000>;
431 + hysteresis = <2000>;
432 + type = "critical_high";
436 + temperature = <105000>;
437 + hysteresis = <2000>;
438 + type = "configurable_hi";
442 + temperature = <95000>;
443 + hysteresis = <2000>;
444 + type = "configurable_lo";
449 + hysteresis = <2000>;
450 + type = "critical_low";
455 + tsens_tz_sensor10 {
456 + polling-delay-passive = <0>;
457 + polling-delay = <0>;
458 + thermal-sensors = <&tsens 10>;
462 + temperature = <125000>;
463 + hysteresis = <2000>;
464 + type = "critical_high";
468 + temperature = <105000>;
469 + hysteresis = <2000>;
470 + type = "configurable_hi";
474 + temperature = <95000>;
475 + hysteresis = <2000>;
476 + type = "configurable_lo";
481 + hysteresis = <2000>;
482 + type = "critical_low";
493 + compatible = "qcom,fab-scaling";
494 + clocks = <&rpmcc RPM_APPS_FABRIC_A_CLK>, <&rpmcc RPM_EBI1_A_CLK>;
495 + clock-names = "apps-fab-clk", "ddr-fab-clk";
496 + fab_freq_high = <533000000>;
497 + fab_freq_nominal = <400000000>;
498 + cpu_freq_threshold = <1000000000>;
503 compatible = "qcom,scm-ipq806x", "qcom,scm";
505 reg-names = "lpass-lpaif";
508 + qfprom: qfprom@700000 {
509 + compatible = "qcom,qfprom", "syscon";
510 + reg = <0x700000 0x1000>;
511 + #address-cells = <1>;
514 + tsens_calib: calib@400 {
517 + tsens_backup: backup@410 {
520 + speedbin_efuse: speedbin@0c0 {
526 + compatible = "qcom,rpm-ipq8064";
527 + reg = <0x108000 0x1000>;
528 + qcom,ipc = <&l2cc 0x8 2>;
530 + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
531 + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
532 + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
533 + interrupt-names = "ack", "err", "wakeup";
535 + clocks = <&gcc RPM_MSG_RAM_H_CLK>;
536 + clock-names = "ram";
538 + #address-cells = <1>;
541 + rpmcc: clock-controller {
542 + compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
543 + #clock-cells = <1>;
547 + compatible = "qcom,rpm-smb208-regulators";
550 + regulator-min-microvolt = <1050000>;
551 + regulator-max-microvolt = <1150000>;
553 + qcom,switch-mode-frequency = <1200000>;
557 + regulator-min-microvolt = <1050000>;
558 + regulator-max-microvolt = <1150000>;
560 + qcom,switch-mode-frequency = <1200000>;
564 + regulator-min-microvolt = < 800000>;
565 + regulator-max-microvolt = <1250000>;
567 + qcom,switch-mode-frequency = <1200000>;
571 + regulator-min-microvolt = < 800000>;
572 + regulator-max-microvolt = <1250000>;
574 + qcom,switch-mode-frequency = <1200000>;
580 + compatible = "qcom,prng";
581 + reg = <0x1a500000 0x200>;
582 + clocks = <&gcc PRNG_CLK>;
583 + clock-names = "core";
586 qcom_pinmux: pinmux@800000 {
587 compatible = "qcom,ipq8064-pinctrl";
588 reg = <0x800000 0x4000>;
593 + i2c4_pins: i2c4_pinmux {
595 + pins = "gpio12", "gpio13";
596 + function = "gsbi4";
597 + drive-strength = <12>;
604 pins = "gpio18", "gpio19", "gpio21";
609 + nand_pins: nand_pins {
611 + pins = "gpio34", "gpio35", "gpio36",
612 + "gpio37", "gpio38";
614 + drive-strength = <10>;
621 + drive-strength = <10>;
626 + pins = "gpio40", "gpio41", "gpio42",
627 + "gpio43", "gpio44", "gpio45",
628 + "gpio46", "gpio47";
630 + drive-strength = <10>;
635 + mdio0_pins: mdio0_pins {
637 + pins = "gpio0", "gpio1";
639 + drive-strength = <8>;
644 + rgmii2_pins: rgmii2_pins {
646 + pins = "gpio27", "gpio28", "gpio29",
647 + "gpio30", "gpio31", "gpio32",
648 + "gpio51", "gpio52", "gpio59",
649 + "gpio60", "gpio61", "gpio62";
650 + function = "rgmii2";
651 + drive-strength = <8>;
656 leds_pins: leds_pins {
658 pins = "gpio7", "gpio8", "gpio9",
660 clock-output-names = "acpu1_aux";
663 + l2cc: clock-controller@2011000 {
664 + compatible = "qcom,kpss-gcc", "syscon";
665 + reg = <0x2011000 0x1000>;
666 + clock-output-names = "acpu_l2_aux";
669 + kraitcc: clock-controller {
670 + compatible = "qcom,krait-cc-v1";
671 + #clock-cells = <1>;
674 saw0: regulator@2089000 {
675 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
676 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
681 + saw_l2: regulator@02012000 {
682 + compatible = "qcom,saw2", "syscon";
683 + reg = <0x02012000 0x1000>;
687 + sic_non_secure: sic-non-secure@12100000 {
688 + compatible = "syscon";
689 + reg = <0x12100000 0x10000>;
692 gsbi2: gsbi@12480000 {
693 compatible = "qcom,gsbi-v1.0.0";
695 @@ -436,6 +1060,15 @@
696 #power-domain-cells = <1>;
699 + tsens: thermal-sensor@900000 {
700 + compatible = "qcom,ipq8064-tsens";
701 + reg = <0x900000 0x3680>;
702 + nvmem-cells = <&tsens_calib>, <&tsens_backup>;
703 + nvmem-cell-names = "calib", "calib_backup";
704 + interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
705 + #thermal-sensor-cells = <1>;
708 tcsr: syscon@1a400000 {
709 compatible = "qcom,tcsr-ipq8064", "syscon";
710 reg = <0x1a400000 0x100>;
711 @@ -448,6 +1081,95 @@
715 + sfpb_mutex_block: syscon@1200600 {
716 + compatible = "syscon";
717 + reg = <0x01200600 0x100>;
720 + hs_phy_0: hs_phy_0 {
721 + compatible = "qcom,ipq806x-usb-phy-hs";
722 + reg = <0x110f8800 0x30>;
723 + clocks = <&gcc USB30_0_UTMI_CLK>;
724 + clock-names = "ref";
728 + ss_phy_0: ss_phy_0 {
729 + compatible = "qcom,ipq806x-usb-phy-ss";
730 + reg = <0x110f8830 0x30>;
731 + clocks = <&gcc USB30_0_MASTER_CLK>;
732 + clock-names = "ref";
736 + usb3_0: usb3@110f8800 {
737 + compatible = "qcom,dwc3", "syscon";
738 + #address-cells = <1>;
740 + reg = <0x110f8800 0x8000>;
741 + clocks = <&gcc USB30_0_MASTER_CLK>;
742 + clock-names = "core";
746 + resets = <&gcc USB30_0_MASTER_RESET>;
747 + reset-names = "master";
749 + status = "disabled";
751 + dwc3_0: dwc3@11000000 {
752 + compatible = "snps,dwc3";
753 + reg = <0x11000000 0xcd00>;
754 + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
755 + phys = <&hs_phy_0>, <&ss_phy_0>;
756 + phy-names = "usb2-phy", "usb3-phy";
758 + snps,dis_u3_susphy_quirk;
762 + hs_phy_1: hs_phy_1 {
763 + compatible = "qcom,ipq806x-usb-phy-hs";
764 + reg = <0x100f8800 0x30>;
765 + clocks = <&gcc USB30_1_UTMI_CLK>;
766 + clock-names = "ref";
770 + ss_phy_1: ss_phy_1 {
771 + compatible = "qcom,ipq806x-usb-phy-ss";
772 + reg = <0x100f8830 0x30>;
773 + clocks = <&gcc USB30_1_MASTER_CLK>;
774 + clock-names = "ref";
778 + usb3_1: usb3@100f8800 {
779 + compatible = "qcom,dwc3", "syscon";
780 + #address-cells = <1>;
782 + reg = <0x100f8800 0x8000>;
783 + clocks = <&gcc USB30_1_MASTER_CLK>;
784 + clock-names = "core";
788 + resets = <&gcc USB30_1_MASTER_RESET>;
789 + reset-names = "master";
791 + status = "disabled";
793 + dwc3_1: dwc3@10000000 {
794 + compatible = "snps,dwc3";
795 + reg = <0x10000000 0xcd00>;
796 + interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
797 + phys = <&hs_phy_1>, <&ss_phy_1>;
798 + phy-names = "usb2-phy", "usb3-phy";
800 + snps,dis_u3_susphy_quirk;
804 pcie0: pci@1b500000 {
805 compatible = "qcom,pcie-ipq8064";
806 reg = <0x1b500000 0x1000
807 @@ -601,6 +1323,167 @@
808 perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
811 + adm_dma: dma@18300000 {
812 + compatible = "qcom,adm";
813 + reg = <0x18300000 0x100000>;
814 + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
817 + clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
818 + clock-names = "core", "iface";
820 + resets = <&gcc ADM0_RESET>,
821 + <&gcc ADM0_PBUS_RESET>,
822 + <&gcc ADM0_C0_RESET>,
823 + <&gcc ADM0_C1_RESET>,
824 + <&gcc ADM0_C2_RESET>;
825 + reset-names = "clk", "pbus", "c0", "c1", "c2";
828 + status = "disabled";
831 + nand_controller: nand-controller@1ac00000 {
832 + compatible = "qcom,ipq806x-nand";
833 + reg = <0x1ac00000 0x800>;
835 + clocks = <&gcc EBI2_CLK>,
836 + <&gcc EBI2_AON_CLK>;
837 + clock-names = "core", "aon";
839 + dmas = <&adm_dma 3>;
840 + dma-names = "rxtx";
841 + qcom,cmd-crci = <15>;
842 + qcom,data-crci = <3>;
844 + status = "disabled";
846 + #address-cells = <1>;
850 + nss_common: syscon@03000000 {
851 + compatible = "syscon";
852 + reg = <0x03000000 0x0000FFFF>;
855 + qsgmii_csr: syscon@1bb00000 {
856 + compatible = "syscon";
857 + reg = <0x1bb00000 0x000001FF>;
860 + stmmac_axi_setup: stmmac-axi-config {
861 + snps,wr_osr_lmt = <7>;
862 + snps,rd_osr_lmt = <7>;
863 + snps,blen = <16 0 0 0 0 0 0>;
866 + mdio0: mdio@37000000 {
867 + #address-cells = <1>;
870 + compatible = "qcom,ipq8064-mdio", "syscon";
871 + reg = <0x37000000 0x200000>;
872 + resets = <&gcc GMAC_CORE1_RESET>;
873 + reset-names = "stmmaceth";
874 + clocks = <&gcc GMAC_CORE1_CLK>;
875 + clock-names = "stmmaceth";
877 + status = "disabled";
880 + gmac0: ethernet@37000000 {
881 + device_type = "network";
882 + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
883 + reg = <0x37000000 0x200000>;
884 + interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
885 + interrupt-names = "macirq";
887 + snps,axi-config = <&stmmac_axi_setup>;
891 + qcom,nss-common = <&nss_common>;
892 + qcom,qsgmii-csr = <&qsgmii_csr>;
894 + clocks = <&gcc GMAC_CORE1_CLK>;
895 + clock-names = "stmmaceth";
897 + resets = <&gcc GMAC_CORE1_RESET>;
898 + reset-names = "stmmaceth";
900 + status = "disabled";
903 + gmac1: ethernet@37200000 {
904 + device_type = "network";
905 + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
906 + reg = <0x37200000 0x200000>;
907 + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
908 + interrupt-names = "macirq";
910 + snps,axi-config = <&stmmac_axi_setup>;
914 + qcom,nss-common = <&nss_common>;
915 + qcom,qsgmii-csr = <&qsgmii_csr>;
917 + clocks = <&gcc GMAC_CORE2_CLK>;
918 + clock-names = "stmmaceth";
920 + resets = <&gcc GMAC_CORE2_RESET>;
921 + reset-names = "stmmaceth";
923 + status = "disabled";
926 + gmac2: ethernet@37400000 {
927 + device_type = "network";
928 + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
929 + reg = <0x37400000 0x200000>;
930 + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
931 + interrupt-names = "macirq";
933 + snps,axi-config = <&stmmac_axi_setup>;
937 + qcom,nss-common = <&nss_common>;
938 + qcom,qsgmii-csr = <&qsgmii_csr>;
940 + clocks = <&gcc GMAC_CORE3_CLK>;
941 + clock-names = "stmmaceth";
943 + resets = <&gcc GMAC_CORE3_RESET>;
944 + reset-names = "stmmaceth";
946 + status = "disabled";
949 + gmac3: ethernet@37600000 {
950 + device_type = "network";
951 + compatible = "qcom,ipq806x-gmac", "snps,dwmac";
952 + reg = <0x37600000 0x200000>;
953 + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
954 + interrupt-names = "macirq";
956 + snps,axi-config = <&stmmac_axi_setup>;
960 + qcom,nss-common = <&nss_common>;
961 + qcom,qsgmii-csr = <&qsgmii_csr>;
963 + clocks = <&gcc GMAC_CORE4_CLK>;
964 + clock-names = "stmmaceth";
966 + resets = <&gcc GMAC_CORE4_RESET>;
967 + reset-names = "stmmaceth";
969 + status = "disabled";
972 vsdcc_fixed: vsdcc-regulator {
973 compatible = "regulator-fixed";
974 regulator-name = "SDCC Power";
975 @@ -676,4 +1559,17 @@
980 + sfpb_mutex: sfpb-mutex {
981 + compatible = "qcom,sfpb-mutex";
982 + syscon = <&sfpb_mutex_block 4 4>;
984 + #hwlock-cells = <1>;
988 + compatible = "qcom,smem";
989 + memory-region = <&smem>;
990 + hwlocks = <&sfpb_mutex 3>;