target/linux/ipq806x/patches-5.4/096-PCI-qcom-Make-sure-PCIe-is-reset-before-init-for-rev.patch

   1 From 1960d75e3251659be8276529e4d01cf6993d9f4a Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Tue, 1 Sep 2020 14:21:44 +0200
   4 Subject: [PATCH] PCI: qcom: Make sure PCIe is reset before init for rev 2.1.0
   5
   6 Qsdk U-Boot can incorrectly leave the PCIe interface in an undefined
   7 state if bootm command is used instead of bootipq. This is caused by the
   8 not deinit of PCIe when bootm is called. Reset the PCIe before init
   9 anyway to fix this U-Boot bug.
  10
  11 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  12 Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
  13 Cc: stable@vger.kernel.org # v4.19+
  14 ---
  15  drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++
  16  1 file changed, 13 insertions(+)
  17
  18 diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
  19 index 3aac77a295ba..82336bbaf8dc 100644
  20 --- a/drivers/pci/controller/dwc/pcie-qcom.c
  21 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
  22 @@ -302,6 +302,9 @@ static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
  23         reset_control_assert(res->por_reset);
  24         reset_control_assert(res->ext_reset);
  25         reset_control_assert(res->phy_reset);
  26 +
  27 +       writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
  28 +
  29         regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
  30  }
  31
  32 @@ -314,6 +317,16 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
  33         u32 val;
  34         int ret;
  35
  36 +       /* reset the PCIe interface as uboot can leave it undefined state */
  37 +       reset_control_assert(res->pci_reset);
  38 +       reset_control_assert(res->axi_reset);
  39 +       reset_control_assert(res->ahb_reset);
  40 +       reset_control_assert(res->por_reset);
  41 +       reset_control_assert(res->ext_reset);
  42 +       reset_control_assert(res->phy_reset);
  43 +
  44 +       writel(1, pcie->parf + PCIE20_PARF_PHY_CTRL);
  45 +
  46         ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
  47         if (ret < 0) {
  48                 dev_err(dev, "cannot enable regulators\n");
  49 --
  50 2.27.0
  51