1 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
2 +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
4 reg = <0x12100000 0x10000>;
7 + gsbi1: gsbi@12440000 {
8 + compatible = "qcom,gsbi-v1.0.0";
10 + reg = <0x12440000 0x100>;
11 + clocks = <&gcc GSBI1_H_CLK>;
12 + clock-names = "iface";
13 + #address-cells = <1>;
16 + status = "disabled";
18 + syscon-tcsr = <&tcsr>;
20 + gsbi1_serial: serial@12450000 {
21 + compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
22 + reg = <0x12450000 0x100>,
24 + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
25 + clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
26 + clock-names = "core", "iface";
27 + status = "disabled";
30 + gsbi1_i2c: i2c@12460000 {
31 + compatible = "qcom,i2c-qup-v1.1.1";
32 + reg = <0x12460000 0x1000>;
33 + interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
34 + clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
35 + clock-names = "core", "iface";
36 + #address-cells = <1>;
38 + status = "disabled";
42 gsbi2: gsbi@12480000 {
43 compatible = "qcom,gsbi-v1.0.0";