1 From fcfbfe373d41b4728ffec075f8f91b6572a88c27 Mon Sep 17 00:00:00 2001
2 From: Ansuel Smith <ansuelsmth@gmail.com>
3 Date: Sat, 30 Apr 2022 07:44:56 +0200
4 Subject: [PATCH 1/3] clk: qcom: clk-hfpll: use poll_timeout macro
6 Use regmap_read_poll_timeout macro instead of do-while structure to tidy
7 things up. Also set a timeout to prevent any sort of system stall.
9 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
10 Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
11 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
12 Link: https://lore.kernel.org/r/20220430054458.31321-2-ansuelsmth@gmail.com
14 drivers/clk/qcom/clk-hfpll.c | 15 +++++++++------
15 1 file changed, 9 insertions(+), 6 deletions(-)
17 --- a/drivers/clk/qcom/clk-hfpll.c
18 +++ b/drivers/clk/qcom/clk-hfpll.c
19 @@ -72,13 +72,16 @@ static void __clk_hfpll_enable(struct cl
20 regmap_update_bits(regmap, hd->mode_reg, PLL_RESET_N, PLL_RESET_N);
22 /* Wait for PLL to lock. */
23 - if (hd->status_reg) {
25 - regmap_read(regmap, hd->status_reg, &val);
26 - } while (!(val & BIT(hd->lock_bit)));
30 + * Busy wait. Should never timeout, we add a timeout to
31 + * prevent any sort of stall.
33 + regmap_read_poll_timeout(regmap, hd->status_reg, val,
34 + !(val & BIT(hd->lock_bit)), 0,
35 + 100 * USEC_PER_MSEC);
40 /* Enable PLL output. */
41 regmap_update_bits(regmap, hd->mode_reg, PLL_OUTCTRL, PLL_OUTCTRL);