1 From 666c1b745e93ccddde841d5057c33f97b29a316a Mon Sep 17 00:00:00 2001
2 From: Christian Marangi <ansuelsmth@gmail.com>
3 Date: Thu, 15 Sep 2022 02:19:28 +0200
4 Subject: [PATCH 3/9] clk: qcom: krait-cc: handle qsb clock defined in DTS
6 qsb fixed clk may be defined in DTS and correctly passed in the clocks
7 list. Add related code to handle this and modify the logic to
8 dynamically read qsb clock frequency.
10 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
12 drivers/clk/qcom/krait-cc.c | 14 +++++++++++---
13 1 file changed, 11 insertions(+), 3 deletions(-)
15 diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
16 index 84f0048961f5..f1d64b16cac3 100644
17 --- a/drivers/clk/qcom/krait-cc.c
18 +++ b/drivers/clk/qcom/krait-cc.c
19 @@ -305,7 +305,7 @@ static int krait_cc_probe(struct platform_device *pdev)
21 struct device *dev = &pdev->dev;
22 const struct of_device_id *id;
23 - unsigned long cur_rate, aux_rate;
24 + unsigned long cur_rate, aux_rate, qsb_rate;
28 @@ -315,11 +315,19 @@ static int krait_cc_probe(struct platform_device *pdev)
32 - /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
33 - clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
35 + * Per Documentation qsb should be provided from DTS.
36 + * To address old implementation, register the fixed clock anyway.
37 + * Rate is 1 because 0 causes problems for __clk_mux_determine_rate
39 + clk = clk_get(dev, "qsb");
41 + clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
45 + qsb_rate = clk_get_rate(clk);
48 clk = clk_register_fixed_factor(dev, "acpu_aux",
49 "gpll0_vote", 0, 1, 2);