1 From 908c361b3c3a139eb3e6a798cb620a6da7514d5c Mon Sep 17 00:00:00 2001
2 From: Christian Marangi <ansuelsmth@gmail.com>
3 Date: Fri, 23 Sep 2022 19:05:39 +0200
4 Subject: [PATCH 2/4] clk: qcom: clk-krait: generilize div functions
6 Generilize div functions and remove hardcode to a divisor of 2.
7 This is just a cleanup and permit to make it more clear the settings of
8 the devisor when used by the krait-cc driver.
10 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
12 drivers/clk/qcom/clk-krait.c | 57 ++++++++++++++++++++----------------
13 drivers/clk/qcom/clk-krait.h | 11 ++++---
14 drivers/clk/qcom/krait-cc.c | 7 +++--
15 3 files changed, 42 insertions(+), 33 deletions(-)
17 --- a/drivers/clk/qcom/clk-krait.c
18 +++ b/drivers/clk/qcom/clk-krait.c
19 @@ -97,53 +97,58 @@ const struct clk_ops krait_mux_clk_ops =
20 EXPORT_SYMBOL_GPL(krait_mux_clk_ops);
22 /* The divider can divide by 2, 4, 6 and 8. But we only really need div-2. */
23 -static long krait_div2_round_rate(struct clk_hw *hw, unsigned long rate,
24 +static long krait_div_round_rate(struct clk_hw *hw, unsigned long rate,
25 unsigned long *parent_rate)
27 - *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw), rate * 2);
28 - return DIV_ROUND_UP(*parent_rate, 2);
29 + struct krait_div_clk *d = to_krait_div_clk(hw);
31 + *parent_rate = clk_hw_round_rate(clk_hw_get_parent(hw),
34 + return DIV_ROUND_UP(*parent_rate, d->divisor);
37 -static int krait_div2_set_rate(struct clk_hw *hw, unsigned long rate,
38 +static int krait_div_set_rate(struct clk_hw *hw, unsigned long rate,
39 unsigned long parent_rate)
41 - struct krait_div2_clk *d = to_krait_div2_clk(hw);
42 + struct krait_div_clk *d = to_krait_div_clk(hw);
43 + u8 div_val = krait_div_to_val(d->divisor);
46 - u32 mask = BIT(d->width) - 1;
49 - mask = mask << (d->shift + LPL_SHIFT) | mask << d->shift;
54 spin_lock_irqsave(&krait_clock_reg_lock, flags);
55 - val = krait_get_l2_indirect_reg(d->offset);
57 - krait_set_l2_indirect_reg(d->offset, val);
58 + regval = krait_get_l2_indirect_reg(d->offset);
60 + regval &= ~(d->mask << d->shift);
61 + regval |= (div_val & d->mask) << d->shift;
64 + regval &= ~(d->mask << (d->shift + LPL_SHIFT));
65 + regval |= (div_val & d->mask) << (d->shift + LPL_SHIFT);
68 + krait_set_l2_indirect_reg(d->offset, regval);
69 spin_unlock_irqrestore(&krait_clock_reg_lock, flags);
75 -krait_div2_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
76 +krait_div_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
78 - struct krait_div2_clk *d = to_krait_div2_clk(hw);
79 - u32 mask = BIT(d->width) - 1;
80 + struct krait_div_clk *d = to_krait_div_clk(hw);
83 div = krait_get_l2_indirect_reg(d->offset);
86 - div = (div + 1) * 2;
89 - return DIV_ROUND_UP(parent_rate, div);
90 + return DIV_ROUND_UP(parent_rate, krait_val_to_div(div));
93 -const struct clk_ops krait_div2_clk_ops = {
94 - .round_rate = krait_div2_round_rate,
95 - .set_rate = krait_div2_set_rate,
96 - .recalc_rate = krait_div2_recalc_rate,
97 +const struct clk_ops krait_div_clk_ops = {
98 + .round_rate = krait_div_round_rate,
99 + .set_rate = krait_div_set_rate,
100 + .recalc_rate = krait_div_recalc_rate,
102 -EXPORT_SYMBOL_GPL(krait_div2_clk_ops);
103 +EXPORT_SYMBOL_GPL(krait_div_clk_ops);
104 --- a/drivers/clk/qcom/clk-krait.h
105 +++ b/drivers/clk/qcom/clk-krait.h
106 @@ -25,17 +25,20 @@ struct krait_mux_clk {
108 extern const struct clk_ops krait_mux_clk_ops;
110 -struct krait_div2_clk {
111 +struct krait_div_clk {
122 -#define to_krait_div2_clk(_hw) container_of(_hw, struct krait_div2_clk, hw)
123 +#define to_krait_div_clk(_hw) container_of(_hw, struct krait_div_clk, hw)
124 +#define krait_div_to_val(_div) ((_div) / 2) - 1
125 +#define krait_val_to_div(_val) ((_val) + 1) * 2
127 -extern const struct clk_ops krait_div2_clk_ops;
128 +extern const struct clk_ops krait_div_clk_ops;
131 --- a/drivers/clk/qcom/krait-cc.c
132 +++ b/drivers/clk/qcom/krait-cc.c
133 @@ -86,11 +86,11 @@ static int krait_notifier_register(struc
134 static struct clk_hw *
135 krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
137 - struct krait_div2_clk *div;
138 + struct krait_div_clk *div;
139 static struct clk_parent_data p_data[1];
140 struct clk_init_data init = {
141 .num_parents = ARRAY_SIZE(p_data),
142 - .ops = &krait_div2_clk_ops,
143 + .ops = &krait_div_clk_ops,
144 .flags = CLK_SET_RATE_PARENT,
147 @@ -101,7 +101,8 @@ krait_add_div(struct device *dev, int id
149 return ERR_PTR(-ENOMEM);
156 div->offset = offset;