target/linux/ipq807x/patches-5.15/0023-v6.0-clk-qcom-ipq8074-add-USB-GDSCs.patch

   1 From ff35d239b7b64f71d7dd9d0ce887647de2cacfcc Mon Sep 17 00:00:00 2001
   2 From: Robert Marko <robimarko@gmail.com>
   3 Date: Sun, 15 May 2022 23:00:46 +0200
   4 Subject: [PATCH] clk: qcom: ipq8074: add USB GDSCs
   5
   6 Add GDSC-s for each of the two USB controllers built-in the IPQ8074.
   7
   8 Signed-off-by: Robert Marko <robimarko@gmail.com>
   9 Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
  10 Link: https://lore.kernel.org/r/20220515210048.483898-9-robimarko@gmail.com
  11 ---
  12  drivers/clk/qcom/Kconfig       |  1 +
  13  drivers/clk/qcom/gcc-ipq8074.c | 24 ++++++++++++++++++++++++
  14  2 files changed, 25 insertions(+)
  15
  16 --- a/drivers/clk/qcom/Kconfig
  17 +++ b/drivers/clk/qcom/Kconfig
  18 @@ -167,6 +167,7 @@ config IPQ_LCC_806X
  19
  20  config IPQ_GCC_8074
  21         tristate "IPQ8074 Global Clock Controller"
  22 +       select QCOM_GDSC
  23         help
  24           Support for global clock controller on ipq8074 devices.
  25           Say Y if you want to use peripheral devices such as UART, SPI,
  26 --- a/drivers/clk/qcom/gcc-ipq8074.c
  27 +++ b/drivers/clk/qcom/gcc-ipq8074.c
  28 @@ -22,6 +22,7 @@
  29  #include "clk-alpha-pll.h"
  30  #include "clk-regmap-divider.h"
  31  #include "clk-regmap-mux.h"
  32 +#include "gdsc.h"
  33  #include "reset.h"
  34
  35  enum {
  36 @@ -4404,6 +4405,22 @@ static struct clk_branch gcc_pcie0_axi_s
  37         },
  38  };
  39
  40 +static struct gdsc usb0_gdsc = {
  41 +       .gdscr = 0x3e078,
  42 +       .pd = {
  43 +               .name = "usb0_gdsc",
  44 +       },
  45 +       .pwrsts = PWRSTS_OFF_ON,
  46 +};
  47 +
  48 +static struct gdsc usb1_gdsc = {
  49 +       .gdscr = 0x3f078,
  50 +       .pd = {
  51 +               .name = "usb1_gdsc",
  52 +       },
  53 +       .pwrsts = PWRSTS_OFF_ON,
  54 +};
  55 +
  56  static const struct alpha_pll_config ubi32_pll_config = {
  57         .l = 0x4e,
  58         .config_ctl_val = 0x200d4aa8,
  59 @@ -4807,6 +4824,11 @@ static const struct qcom_reset_map gcc_i
  60         [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },
  61  };
  62
  63 +static struct gdsc *gcc_ipq8074_gdscs[] = {
  64 +       [USB0_GDSC] = &usb0_gdsc,
  65 +       [USB1_GDSC] = &usb1_gdsc,
  66 +};
  67 +
  68  static const struct of_device_id gcc_ipq8074_match_table[] = {
  69         { .compatible = "qcom,gcc-ipq8074" },
  70         { }
  71 @@ -4829,6 +4851,8 @@ static const struct qcom_cc_desc gcc_ipq
  72         .num_resets = ARRAY_SIZE(gcc_ipq8074_resets),
  73         .clk_hws = gcc_ipq8074_hws,
  74         .num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws),
  75 +       .gdscs = gcc_ipq8074_gdscs,
  76 +       .num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs),
  77  };
  78
  79  static int gcc_ipq8074_probe(struct platform_device *pdev)